mirror of
https://github.com/memtest86plus/memtest86plus.git
synced 2024-11-27 10:00:17 -06:00
1101 lines
32 KiB
C
1101 lines
32 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2020-2022 Martin Whitaker.
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//
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// Derived from an extract of memtest86+ init.c:
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//
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// MemTest86+ V5 Specific code (GPL V2.0)
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// By Samuel DEMEULEMEESTER, sdemeule@memtest.org
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// http://www.canardpc.com - http://www.memtest.org
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// ------------------------------------------------
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// init.c - MemTest-86 Version 3.6
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//
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// Released under version 2 of the Gnu Public License.
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// By Chris Brady
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "cpuid.h"
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#include "io.h"
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#include "tsc.h"
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#include "boot.h"
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#include "config.h"
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#include "pmem.h"
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#include "vmem.h"
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#include "memsize.h"
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#include "hwquirks.h"
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#include "cpuinfo.h"
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//------------------------------------------------------------------------------
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// Constants
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//------------------------------------------------------------------------------
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#define PIT_TICKS_50mS 59659 // PIT clock is 1.193182MHz
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#define BENCH_MIN_START_ADR 0x1000000 // 16MB
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//------------------------------------------------------------------------------
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// Public Variables
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//------------------------------------------------------------------------------
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const char *cpu_model = NULL;
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uint16_t imc_type = 0;
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int l1_cache = 0;
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int l2_cache = 0;
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int l3_cache = 0;
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uint32_t l1_cache_speed = 0;
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uint32_t l2_cache_speed = 0;
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uint32_t l3_cache_speed = 0;
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uint32_t ram_speed = 0;
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bool no_temperature = false;
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uint32_t clks_per_msec = 0;
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//------------------------------------------------------------------------------
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// Private Functions
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//------------------------------------------------------------------------------
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static void determine_cache_size()
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{
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switch (cpuid_info.vendor_id.str[0]) {
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case 'A':
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// AMD Processors (easy!)
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l1_cache = cpuid_info.cache_info.l1_d_size;
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l2_cache = cpuid_info.cache_info.l2_size;
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l3_cache = cpuid_info.cache_info.l3_size;
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l3_cache *= 512;
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break;
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case 'C':
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// Zhaoxin CPU only
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if (cpuid_info.version.family != 7) {
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break;
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}
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/* fall through */
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case 'G':
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// Intel Processors
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l1_cache = 0;
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l2_cache = 0;
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l3_cache = 0;
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// Use CPUID(4) if it is available.
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if (cpuid_info.max_cpuid > 3) {
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cpuid4_eax_t eax;
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cpuid4_ebx_t ebx;
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cpuid4_ecx_t ecx;
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uint32_t dummy;
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// Loop through the cache leaves.
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int i = 0;
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do {
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cpuid(4, i, &eax.raw, &ebx.raw, &ecx.raw, &dummy);
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// Check for a valid cache type...
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if (eax.ctype == 1 || eax.ctype == 3) {
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// Compute the cache size
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int size = (ecx.number_of_sets + 1)
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* (ebx.coherency_line_size + 1)
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* (ebx.physical_line_partition + 1)
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* (ebx.ways_of_associativity + 1);
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size /= 1024;
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switch (eax.level) {
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case 1:
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l1_cache += size;
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break;
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case 2:
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l2_cache += size;
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break;
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case 3:
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l3_cache += size;
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break;
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default:
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break;
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}
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}
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i++;
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} while (eax.ctype != 0);
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return;
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}
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// No CPUID(4) so we use the older CPUID(2) method.
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uint32_t v[4];
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uint8_t *dp = (uint8_t *)v;
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int i = 0;
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do {
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cpuid(2, 0, &v[0], &v[1], &v[2], &v[3]);
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// If bit 31 is set, this is an unknown format.
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for (int j = 0; j < 4; j++) {
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if (v[j] & (1 << 31)) {
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v[j] = 0;
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}
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}
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// Byte 0 is level count, not a descriptor.
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for (int j = 1; j < 16; j++) {
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switch (dp[j]) {
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case 0x6:
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case 0xa:
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case 0x66:
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l1_cache += 8;
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break;
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case 0x8:
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case 0xc:
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case 0xd:
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case 0x60:
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case 0x67:
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l1_cache += 16;
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break;
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case 0xe:
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l1_cache += 24;
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break;
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case 0x9:
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case 0x2c:
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case 0x30:
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case 0x68:
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l1_cache += 32;
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break;
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case 0x39:
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case 0x3b:
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case 0x41:
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case 0x79:
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l2_cache += 128;
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break;
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case 0x3a:
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l2_cache += 192;
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break;
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case 0x21:
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case 0x3c:
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case 0x3f:
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case 0x42:
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case 0x7a:
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case 0x82:
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l2_cache += 256;
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break;
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case 0x3d:
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l2_cache += 384;
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break;
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case 0x3e:
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case 0x43:
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case 0x7b:
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case 0x7f:
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case 0x80:
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case 0x83:
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case 0x86:
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l2_cache += 512;
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break;
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case 0x44:
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case 0x78:
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case 0x7c:
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case 0x84:
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case 0x87:
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l2_cache += 1024;
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break;
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case 0x45:
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case 0x7d:
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case 0x85:
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l2_cache += 2048;
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break;
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case 0x48:
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l2_cache += 3072;
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break;
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case 0x4e:
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l2_cache += 6144;
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break;
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case 0x23:
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case 0xd0:
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l3_cache += 512;
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break;
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case 0xd1:
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case 0xd6:
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l3_cache += 1024;
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break;
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case 0x25:
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case 0xd2:
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case 0xd7:
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case 0xdc:
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case 0xe2:
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l3_cache += 2048;
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break;
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case 0x29:
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case 0x46:
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case 0x49:
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case 0xd8:
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case 0xdd:
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case 0xe3:
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l3_cache += 4096;
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break;
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case 0x4a:
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l3_cache += 6144;
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break;
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case 0x47:
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case 0x4b:
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case 0xde:
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case 0xe4:
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l3_cache += 8192;
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break;
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case 0x4c:
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case 0xea:
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l3_cache += 12288;
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break;
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case 0x4d:
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l3_cache += 16384;
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break;
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case 0xeb:
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l3_cache += 18432;
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break;
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case 0xec:
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l3_cache += 24576;
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break;
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default:
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break;
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}
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}
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} while (++i < dp[0]);
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break;
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default:
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break;
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}
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}
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static void determine_imc(void)
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{
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// Check AMD IMC
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if (cpuid_info.vendor_id.str[0] == 'A' && cpuid_info.version.family == 0xF)
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{
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switch (cpuid_info.version.extendedFamily)
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{
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case 0x0:
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imc_type = IMC_K8; // Old K8
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break;
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case 0x1:
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case 0x2:
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imc_type = IMC_K10; // K10 (Family 10h & 11h)
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break;
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case 0x3:
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imc_type = IMC_K12; // A-Series APU (Family 12h)
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break;
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case 0x5:
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imc_type = IMC_K14; // C- / E- / Z- Series APU (Family 14h)
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break;
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case 0x6:
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imc_type = IMC_K15; // FX Series (Family 15h)
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break;
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case 0x7:
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imc_type = IMC_K16; // Kabini & related (Family 16h)
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break;
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case 0x8:
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imc_type = IMC_K17; // Zen & Zen2 (Family 17h)
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break;
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case 0x9:
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imc_type = IMC_K18; // Hygon (Family 18h)
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break;
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case 0xA:
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if(cpuid_info.version.extendedModel == 5) {
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imc_type = IMC_K19_CZN; // AMD Cezanne APU (Model 0x50-5F - Family 19h)
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} else {
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imc_type = IMC_K19; // Zen3 & Zen4 (Family 19h)
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}
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default:
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break;
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}
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return;
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}
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// Check Intel IMC
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if (cpuid_info.vendor_id.str[0] == 'G' && cpuid_info.version.family == 6 && cpuid_info.version.extendedModel)
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{
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switch (cpuid_info.version.model) {
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case 0x5:
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switch (cpuid_info.version.extendedModel) {
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case 2:
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imc_type = IMC_NHM; // Core i3/i5 1st Gen 45 nm (Nehalem/Bloomfield)
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break;
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case 3:
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no_temperature = true; // Atom Clover Trail
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break;
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case 4:
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imc_type = IMC_HSW_ULT; // Core 4th Gen (Haswell-ULT)
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break;
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case 5:
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imc_type = IMC_SKL_SP; // Skylake/Cascade Lake/Cooper Lake (Server)
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break;
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default:
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break;
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}
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break;
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case 0x6:
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switch (cpuid_info.version.extendedModel) {
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case 3:
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imc_type = IMC_CDT; // Atom Cedar Trail
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no_temperature = true;
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break;
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case 4:
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imc_type = IMC_HSW; // Core 4th Gen (Haswell w/ GT3e)
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break;
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case 5:
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imc_type = IMC_BDW_DE; // Broadwell-DE (Server)
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break;
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case 6:
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imc_type = IMC_CNL; // Cannon Lake
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break;
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default:
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break;
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}
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break;
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case 0x7:
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switch (cpuid_info.version.extendedModel) {
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case 0x3:
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imc_type = IMC_BYT; // Atom Bay Trail
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break;
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case 0x4:
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imc_type = IMC_BDW; // Core 5th Gen (Broadwell)
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break;
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case 0x9:
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imc_type = IMC_ADL; // Core 12th Gen (Alder Lake-P)
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break;
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case 0xA:
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imc_type = IMC_RKL; // Core 11th Gen (Rocket Lake)
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break;
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case 0xB:
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imc_type = IMC_RPL; // Core 13th Gen (Raptor Lake)
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break;
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default:
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break;
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}
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break;
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case 0xA:
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switch (cpuid_info.version.extendedModel) {
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case 0x1:
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imc_type = IMC_NHM_E; // Core i7 1st Gen 45 nm (NHME)
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break;
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case 0x2:
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imc_type = IMC_SNB; // Core 2nd Gen (Sandy Bridge)
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break;
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case 0x3:
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imc_type = IMC_IVB; // Core 3rd Gen (Ivy Bridge)
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break;
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case 0x6:
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imc_type = IMC_ICL_SP; // Ice Lake-SP/DE (Server)
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break;
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case 0x9:
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imc_type = IMC_ADL; // Core 12th Gen (Alder Lake-S)
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break;
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default:
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break;
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}
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break;
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case 0xC:
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switch (cpuid_info.version.extendedModel) {
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case 0x1:
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if (cpuid_info.version.stepping > 9) {
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imc_type = 0x0008; // Atom PineView
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}
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no_temperature = true;
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break;
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case 0x2:
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imc_type = IMC_WMR; // Core i7 1st Gen 32 nm (Westmere)
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break;
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case 0x3:
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imc_type = IMC_HSW; // Core 4th Gen (Haswell)
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break;
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case 0x8:
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imc_type = IMC_TGL; // Core 11th Gen (Tiger Lake-U)
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break;
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default:
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break;
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}
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break;
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case 0xD:
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switch (cpuid_info.version.extendedModel) {
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case 0x2:
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imc_type = IMC_SNB_E; // Core 2nd Gen (Sandy Bridge-E)
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break;
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case 0x7:
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imc_type = IMC_ICL; // Core 10th Gen (IceLake-Y)
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break;
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case 0x8:
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imc_type = IMC_TGL; // Core 11th Gen (Tiger Lake-Y)
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break;
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default:
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break;
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}
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break;
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case 0xE:
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switch (cpuid_info.version.extendedModel) {
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case 0x1:
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imc_type = IMC_NHM; // Core i7 1st Gen 45 nm (Nehalem/Bloomfield)
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break;
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case 0x2:
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imc_type = IMC_SNB_E; // Core 2nd Gen (Sandy Bridge-E)
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break;
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case 0x3:
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imc_type = IMC_IVB_E; // Core 3rd Gen (Ivy Bridge-E)
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break;
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case 0x4:
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imc_type = IMC_SKL_UY; // Core 6th Gen (Sky Lake-U/Y)
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break;
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case 0x5:
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imc_type = IMC_SKL; // Core 6th Gen (Sky Lake-S/H/E)
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break;
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case 0x7:
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imc_type = IMC_ICL; // Core 10th Gen (IceLake-U)
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break;
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case 0x8:
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imc_type = IMC_KBL_UY; // Core 7/8/9th Gen (Kaby/Coffee/Comet/Amber Lake-U/Y)
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break;
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case 0x9:
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imc_type = IMC_KBL; // Core 7/8/9th Gen (Kaby/Coffee/Comet Lake)
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break;
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default:
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break;
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}
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break;
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case 0xF:
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switch (cpuid_info.version.extendedModel) {
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case 0x3:
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imc_type = IMC_HSW_E; // Core 3rd Gen (Haswell-E)
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break;
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case 0x4:
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imc_type = IMC_BDW_E; // Broadwell-E (Server)
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break;
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case 0x8:
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imc_type = IMC_SPR; // Sapphire Rapids (Server)
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return;
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}
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}
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static void determine_cpu_model(void)
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{
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// If we can get a brand string use it, and we are done.
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if (cpuid_info.max_xcpuid >= 0x80000004) {
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cpu_model = cpuid_info.brand_id.str;
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determine_imc();
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return;
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}
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// The brand string is not available so we need to figure out CPU what we have.
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switch (cpuid_info.vendor_id.str[0]) {
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case 'A':
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// AMD Processors
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switch (cpuid_info.version.family) {
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case 4:
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switch (cpuid_info.version.model) {
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case 3:
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cpu_model = "AMD 486DX2";
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break;
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case 7:
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cpu_model = "AMD 486DX2-WB";
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break;
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case 8:
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cpu_model = "AMD 486DX4";
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break;
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case 9:
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cpu_model = "AMD 486DX4-WB";
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break;
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case 14:
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cpu_model = "AMD 5x86-WT";
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break;
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case 15:
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cpu_model = "AMD 5x86-WB";
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break;
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default:
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break;
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}
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break;
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case 5:
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switch (cpuid_info.version.model) {
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case 0:
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case 1:
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case 2:
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case 3:
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cpu_model = "AMD K5";
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l1_cache = 8;
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break;
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case 6:
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case 7:
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cpu_model = "AMD K6";
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break;
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case 8:
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cpu_model = "AMD K6-2";
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break;
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case 9:
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cpu_model = "AMD K6-III";
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break;
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case 13:
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cpu_model = "AMD K6-III+";
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break;
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default:
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break;
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}
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break;
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case 6:
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switch (cpuid_info.version.model) {
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case 1:
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cpu_model = "AMD Athlon (0.25)";
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break;
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case 2:
|
|
case 4:
|
|
cpu_model = "AMD Athlon (0.18)";
|
|
break;
|
|
case 6:
|
|
if (l2_cache == 64) {
|
|
cpu_model = "AMD Duron (0.18)";
|
|
} else {
|
|
cpu_model = "Athlon XP (0.18)";
|
|
}
|
|
break;
|
|
case 8:
|
|
case 10:
|
|
if (l2_cache == 64) {
|
|
cpu_model = "AMD Duron (0.13)";
|
|
} else {
|
|
cpu_model = "Athlon XP (0.13)";
|
|
}
|
|
break;
|
|
case 3:
|
|
case 7:
|
|
cpu_model = "AMD Duron";
|
|
// Duron stepping 0 CPUID for L2 is broken (AMD errata T13)
|
|
if (cpuid_info.version.stepping == 0) {
|
|
// Hard code the right L2 size.
|
|
l2_cache = 64;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
// All AMD family values >= 10 have the Brand ID feature so we don't need to find the CPU type.
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 'G':
|
|
// Transmeta Processors - vendor_id starts with "GenuineTMx86"
|
|
if (cpuid_info.vendor_id.str[7] == 'T' ) {
|
|
if (cpuid_info.version.family == 5) {
|
|
cpu_model = "TM 5x00";
|
|
} else if (cpuid_info.version.family == 15) {
|
|
cpu_model = "TM 8x00";
|
|
}
|
|
l1_cache = cpuid_info.cache_info.l1_i_size + cpuid_info.cache_info.l1_d_size;
|
|
l2_cache = cpuid_info.cache_info.l2_size;
|
|
break;
|
|
}
|
|
// Intel Processors - vendor_id starts with "GenuineIntel"
|
|
switch (cpuid_info.version.family) {
|
|
case 4:
|
|
switch (cpuid_info.version.model) {
|
|
case 0:
|
|
case 1:
|
|
cpu_model = "Intel 486DX";
|
|
break;
|
|
case 2:
|
|
cpu_model = "Intel 486SX";
|
|
break;
|
|
case 3:
|
|
cpu_model = "Intel 486DX2";
|
|
break;
|
|
case 4:
|
|
cpu_model = "Intel 486SL";
|
|
break;
|
|
case 5:
|
|
cpu_model = "Intel 486SX2";
|
|
break;
|
|
case 7:
|
|
cpu_model = "Intel 486DX2-WB";
|
|
break;
|
|
case 8:
|
|
cpu_model = "Intel 486DX4";
|
|
break;
|
|
case 9:
|
|
cpu_model = "Intel 486DX4-WB";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 5:
|
|
switch (cpuid_info.version.model) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
case 7:
|
|
cpu_model = "Pentium";
|
|
if (l1_cache == 0) {
|
|
l1_cache = 8;
|
|
}
|
|
break;
|
|
case 4:
|
|
case 8:
|
|
cpu_model = "Pentium-MMX";
|
|
if (l1_cache == 0) {
|
|
l1_cache = 16;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 6:
|
|
switch (cpuid_info.version.model) {
|
|
case 0:
|
|
case 1:
|
|
cpu_model = "Pentium Pro";
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
cpu_model = "Pentium II";
|
|
break;
|
|
case 5:
|
|
if (l2_cache == 0) {
|
|
cpu_model = "Celeron";
|
|
} else {
|
|
cpu_model = "Pentium II";
|
|
}
|
|
break;
|
|
case 6:
|
|
if (l2_cache == 128) {
|
|
cpu_model = "Celeron";
|
|
} else {
|
|
cpu_model = "Pentium II";
|
|
}
|
|
break;
|
|
case 7:
|
|
case 8:
|
|
case 11:
|
|
if (l2_cache == 128) {
|
|
cpu_model = "Celeron";
|
|
} else {
|
|
cpu_model = "Pentium III";
|
|
}
|
|
break;
|
|
case 9:
|
|
if (l2_cache == 512) {
|
|
cpu_model = "Celeron M (0.13)";
|
|
} else {
|
|
cpu_model = "Pentium M (0.13)";
|
|
}
|
|
break;
|
|
case 10:
|
|
cpu_model = "Pentium III Xeon";
|
|
break;
|
|
case 12:
|
|
l1_cache = 24;
|
|
cpu_model = "Atom (0.045)";
|
|
break;
|
|
case 13:
|
|
if (l2_cache == 1024) {
|
|
cpu_model = "Celeron M (0.09)";
|
|
} else {
|
|
cpu_model = "Pentium M (0.09)";
|
|
}
|
|
break;
|
|
case 14:
|
|
cpu_model = "Intel Core";
|
|
break;
|
|
case 15:
|
|
if (l2_cache == 1024) {
|
|
cpu_model = "Pentium E";
|
|
} else {
|
|
cpu_model = "Intel Core 2";
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 15:
|
|
switch (cpuid_info.version.model) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
if (l2_cache == 128) {
|
|
cpu_model = "Celeron";
|
|
} else {
|
|
cpu_model = "Pentium 4";
|
|
}
|
|
break;
|
|
case 3:
|
|
case 4:
|
|
if (l2_cache == 256) {
|
|
cpu_model = "Celeron (0.09)";
|
|
} else {
|
|
cpu_model = "Pentium 4 (0.09)";
|
|
}
|
|
break;
|
|
case 6:
|
|
cpu_model = "Pentium D (65nm)";
|
|
break;
|
|
default:
|
|
cpu_model = "Unknown Intel";
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 'C':
|
|
// VIA/Cyrix/Centaur Processors with CPUID
|
|
if (cpuid_info.vendor_id.str[1] == 'e' ) {
|
|
// CentaurHauls
|
|
l1_cache = cpuid_info.cache_info.l1_i_size + cpuid_info.cache_info.l1_d_size;
|
|
l2_cache = cpuid_info.cache_info.l2_size >> 8;
|
|
switch (cpuid_info.version.family) {
|
|
case 5:
|
|
cpu_model = "Centaur 5x86";
|
|
break;
|
|
case 6: // VIA C3
|
|
switch (cpuid_info.version.model) {
|
|
case 10:
|
|
cpu_model = "VIA C7 (C5J)";
|
|
l1_cache = 64;
|
|
l2_cache = 128;
|
|
break;
|
|
case 13:
|
|
cpu_model = "VIA C7 (C5R)";
|
|
l1_cache = 64;
|
|
l2_cache = 128;
|
|
break;
|
|
case 15:
|
|
cpu_model = "VIA Isaiah (CN)";
|
|
l1_cache = 64;
|
|
l2_cache = 128;
|
|
break;
|
|
default:
|
|
if (cpuid_info.version.stepping < 8) {
|
|
cpu_model = "VIA C3 Samuel2";
|
|
} else {
|
|
cpu_model = "VIA C3 Eden";
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
} else { /* CyrixInstead */
|
|
switch (cpuid_info.version.family) {
|
|
case 5:
|
|
switch (cpuid_info.version.model) {
|
|
case 0:
|
|
cpu_model = "Cyrix 6x86MX/MII";
|
|
break;
|
|
case 4:
|
|
cpu_model = "Cyrix GXm";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 6: // VIA C3
|
|
switch (cpuid_info.version.model) {
|
|
case 6:
|
|
cpu_model = "Cyrix III";
|
|
break;
|
|
case 7:
|
|
if (cpuid_info.version.stepping < 8) {
|
|
cpu_model = "VIA C3 Samuel2";
|
|
} else {
|
|
cpu_model = "VIA C3 Ezra-T";
|
|
}
|
|
break;
|
|
case 8:
|
|
cpu_model = "VIA C3 Ezra-T";
|
|
break;
|
|
case 9:
|
|
cpu_model = "VIA C3 Nehemiah";
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
// L1 = L2 = 64 KB from Cyrix III to Nehemiah
|
|
l1_cache = 64;
|
|
l2_cache = 64;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
// Unknown processor - make a guess at the family.
|
|
switch (cpuid_info.version.family) {
|
|
case 5:
|
|
cpu_model = "586";
|
|
break;
|
|
case 6:
|
|
cpu_model = "686";
|
|
break;
|
|
default:
|
|
cpu_model = "Unidentified Processor";
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void measure_cpu_speed(void)
|
|
{
|
|
if (cpuid_info.flags.rdtsc == 0) {
|
|
return;
|
|
}
|
|
|
|
// Set up timer
|
|
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
|
|
outb(0xb0, 0x43);
|
|
outb(PIT_TICKS_50mS & 0xff, 0x42);
|
|
outb(PIT_TICKS_50mS >> 8, 0x42);
|
|
|
|
uint32_t start_time;
|
|
rdtscl(start_time);
|
|
|
|
int loops = 0;
|
|
do {
|
|
loops++;
|
|
} while ((inb(0x61) & 0x20) == 0);
|
|
|
|
uint32_t end_time;
|
|
rdtscl(end_time);
|
|
|
|
uint32_t run_time = end_time - start_time;
|
|
|
|
// Make sure we have a credible result
|
|
if (loops >= 4 && run_time >= 50000) {
|
|
clks_per_msec = run_time / 50;
|
|
}
|
|
}
|
|
|
|
static uint32_t memspeed(uintptr_t src, uint32_t len, int iter)
|
|
{
|
|
uintptr_t dst;
|
|
uintptr_t wlen;
|
|
uint64_t start_time, end_time, run_time_clk, overhead;
|
|
int i;
|
|
|
|
dst = src + len;
|
|
|
|
#ifdef __x86_64__
|
|
wlen = len / 8;
|
|
// Get number of clock cycles due to overhead
|
|
start_time = get_tsc();
|
|
for (i = 0; i < iter; i++) {
|
|
__asm__ __volatile__ (
|
|
"movq %0,%%rsi\n\t" \
|
|
"movq %1,%%rdi\n\t" \
|
|
"movq %2,%%rcx\n\t" \
|
|
"cld\n\t" \
|
|
"rep\n\t" \
|
|
"movsq\n\t" \
|
|
:: "g" (src), "g" (dst), "g" (0)
|
|
: "rsi", "rdi", "rcx"
|
|
);
|
|
}
|
|
end_time = get_tsc();
|
|
|
|
overhead = (end_time - start_time);
|
|
|
|
// Prime the cache
|
|
__asm__ __volatile__ (
|
|
"movq %0,%%rsi\n\t" \
|
|
"movq %1,%%rdi\n\t" \
|
|
"movq %2,%%rcx\n\t" \
|
|
"cld\n\t" \
|
|
"rep\n\t" \
|
|
"movsq\n\t" \
|
|
:: "g" (src), "g" (dst), "g" (wlen)
|
|
: "rsi", "rdi", "rcx"
|
|
);
|
|
|
|
// Write these bytes
|
|
start_time = get_tsc();
|
|
for (i = 0; i < iter; i++) {
|
|
__asm__ __volatile__ (
|
|
"movq %0,%%rsi\n\t" \
|
|
"movq %1,%%rdi\n\t" \
|
|
"movq %2,%%rcx\n\t" \
|
|
"cld\n\t" \
|
|
"rep\n\t" \
|
|
"movsq\n\t" \
|
|
:: "g" (src), "g" (dst), "g" (wlen)
|
|
: "rsi", "rdi", "rcx"
|
|
);
|
|
}
|
|
end_time = get_tsc();
|
|
#else
|
|
wlen = len / 4;
|
|
// Get number of clock cycles due to overhead
|
|
start_time = get_tsc();
|
|
for (i = 0; i < iter; i++) {
|
|
__asm__ __volatile__ (
|
|
"movl %0,%%esi\n\t" \
|
|
"movl %1,%%edi\n\t" \
|
|
"movl %2,%%ecx\n\t" \
|
|
"cld\n\t" \
|
|
"rep\n\t" \
|
|
"movsl\n\t" \
|
|
:: "g" (src), "g" (dst), "g" (0)
|
|
: "esi", "edi", "ecx"
|
|
);
|
|
}
|
|
end_time = get_tsc();
|
|
|
|
overhead = (end_time - start_time);
|
|
|
|
// Prime the cache
|
|
__asm__ __volatile__ (
|
|
"movl %0,%%esi\n\t" \
|
|
"movl %1,%%edi\n\t" \
|
|
"movl %2,%%ecx\n\t" \
|
|
"cld\n\t" \
|
|
"rep\n\t" \
|
|
"movsl\n\t" \
|
|
:: "g" (src), "g" (dst), "g" (wlen)
|
|
: "esi", "edi", "ecx"
|
|
);
|
|
|
|
// Write these bytes
|
|
start_time = get_tsc();
|
|
for (i = 0; i < iter; i++) {
|
|
__asm__ __volatile__ (
|
|
"movl %0,%%esi\n\t" \
|
|
"movl %1,%%edi\n\t" \
|
|
"movl %2,%%ecx\n\t" \
|
|
"cld\n\t" \
|
|
"rep\n\t" \
|
|
"movsl\n\t" \
|
|
:: "g" (src), "g" (dst), "g" (wlen)
|
|
: "esi", "edi", "ecx"
|
|
);
|
|
}
|
|
end_time = get_tsc();
|
|
#endif
|
|
|
|
if ((end_time - start_time) > overhead) {
|
|
run_time_clk = (end_time - start_time) - overhead;
|
|
} else {
|
|
return 0;
|
|
}
|
|
|
|
run_time_clk = ((len * iter) / (double)run_time_clk) * clks_per_msec * 2;
|
|
|
|
return run_time_clk;
|
|
}
|
|
|
|
static void measure_memory_bandwidth(void)
|
|
{
|
|
uintptr_t bench_start_adr = 0;
|
|
size_t mem_test_len;
|
|
|
|
if (l3_cache) {
|
|
mem_test_len = 4*l3_cache*1024;
|
|
} else if (l2_cache) {
|
|
mem_test_len = 4*l2_cache*1024;
|
|
} else {
|
|
return; // If we're not able to detect L2, don't start benchmark
|
|
}
|
|
|
|
// Locate enough free space for tests. We require the space to be mapped into
|
|
// our virtual address space, which limits us to the first 2GB.
|
|
for (int i = 0; i < pm_map_size && pm_map[i].start < VM_PINNED_SIZE; i++) {
|
|
uintptr_t try_start = pm_map[i].start << PAGE_SHIFT;
|
|
uintptr_t try_end = try_start + mem_test_len * 2;
|
|
|
|
// No start address below BENCH_MIN_START_ADR
|
|
if (try_start < BENCH_MIN_START_ADR) {
|
|
if ((pm_map[i].end << PAGE_SHIFT) >= (BENCH_MIN_START_ADR + mem_test_len * 2)) {
|
|
try_start = BENCH_MIN_START_ADR;
|
|
try_end = BENCH_MIN_START_ADR + mem_test_len * 2;
|
|
} else {
|
|
continue;
|
|
}
|
|
}
|
|
|
|
// Avoid the memory region where the program is currently located.
|
|
if (try_start < (uintptr_t)_end && try_end > (uintptr_t)_start) {
|
|
try_start = (uintptr_t)_end;
|
|
try_end = try_start + mem_test_len * 2;
|
|
}
|
|
|
|
uintptr_t end_limit = (pm_map[i].end < VM_PINNED_SIZE ? pm_map[i].end : VM_PINNED_SIZE) << PAGE_SHIFT;
|
|
if (try_end <= end_limit) {
|
|
bench_start_adr = try_start;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (bench_start_adr == 0) {
|
|
return;
|
|
}
|
|
|
|
// Measure L1 BW using 1/3rd of the total L1 cache size
|
|
if (l1_cache) {
|
|
l1_cache_speed = memspeed(bench_start_adr, (l1_cache/3)*1024, 50);
|
|
}
|
|
|
|
// Measure L2 BW using half the L2 cache size
|
|
if (l2_cache) {
|
|
l2_cache_speed = memspeed(bench_start_adr, l2_cache/2*1024, 50);
|
|
}
|
|
|
|
// Measure L3 BW using half the L3 cache size
|
|
if (l3_cache) {
|
|
l3_cache_speed = memspeed(bench_start_adr, l3_cache/2*1024, 50);
|
|
}
|
|
|
|
// Measure RAM BW
|
|
ram_speed = memspeed(bench_start_adr, mem_test_len, 25);
|
|
}
|
|
|
|
//------------------------------------------------------------------------------
|
|
// Public Functions
|
|
//------------------------------------------------------------------------------
|
|
|
|
void cpuinfo_init(void)
|
|
{
|
|
// Get cache sizes for most AMD and Intel CPUs. Exceptions for old
|
|
// CPUs are handled in determine_cpu_model().
|
|
determine_cache_size();
|
|
|
|
determine_cpu_model();
|
|
|
|
measure_cpu_speed();
|
|
}
|
|
|
|
void membw_init(void)
|
|
{
|
|
if (quirk.type & QUIRK_TYPE_MEM_SIZE) {
|
|
quirk.process();
|
|
}
|
|
|
|
if(enable_bench) {
|
|
measure_memory_bandwidth();
|
|
}
|
|
}
|