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e86b04a14a
Add a bunch of PCI device IDs and driver indications for other SMBus controllers, so as to avoid other persons having to do that work again. Add support for two PIIX4 devices: the standard PIIX4 PCI device ID, and the ServerWorks CSB5, which has a slight twist. Co-authored-by: Lionel Debroux <lionel_debroux@yahoo.fr> Co-authored-by: Sam Demeulemeester <sam@x86.fr>
130 lines
3.1 KiB
C
130 lines
3.1 KiB
C
#ifndef _SMBUS_H_
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#define _SMBUS_H_
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/**
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* SPDX-License-Identifier: GPL-2.0
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*
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* \file
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*
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* Provides functions for reading SPD via SMBUS
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*
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* Copyright (C) 2004-2022 Samuel Demeulemeester.
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*/
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/* Vendor IDs */
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#define VID_ATI 0x1002
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#define VID_AMD 0x1022
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#define VID_SIS 0x1039
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#define VID_NVIDIA 0x10DE
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#define VID_VIA 0x1106
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#define VID_SERVERWORKS 0x1166
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#define VID_HYGON 0x1D94
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#define VID_INTEL 0x8086
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define SPD5_MR11 11
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/* i801 Hosts Addresses */
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#define SMBHSTSTS smbusbase
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#define SMBHSTCNT smbusbase + 2
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#define SMBHSTCMD smbusbase + 3
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#define SMBHSTADD smbusbase + 4
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#define SMBHSTDAT0 smbusbase + 5
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#define SMBHSTDAT1 smbusbase + 6
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#define SMBBLKDAT smbusbase + 7
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#define SMBPEC smbusbase + 8
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#define SMBAUXSTS smbusbase + 12
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#define SMBAUXCTL smbusbase + 13
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/* i801 Hosts Status register bits */
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#define SMBHSTSTS_BYTE_DONE 0x80
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#define SMBHSTSTS_INUSE_STS 0x40
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#define SMBHSTSTS_SMBALERT_STS 0x20
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#define SMBHSTSTS_FAILED 0x10
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#define SMBHSTSTS_BUS_ERR 0x08
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#define SMBHSTSTS_DEV_ERR 0x04
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#define SMBHSTSTS_INTR 0x02
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#define SMBHSTSTS_HOST_BUSY 0x01
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#define SMBHSTCNT_QUICK 0x00
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#define SMBHSTCNT_BYTE 0x04
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#define SMBHSTCNT_BYTE_DATA 0x08
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#define SMBHSTCNT_WORD_DATA 0x0C
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#define SMBHSTCNT_BLOCK_DATA 0x14
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#define SMBHSTCNT_I2C_BLOCK_DATA 0x18
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#define SMBHSTCNT_LAST_BYTE 0x20
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#define SMBHSTCNT_START 0x40
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/* AMD-Specific constants */
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#define AMD_INDEX_IO_PORT 0xCD6
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#define AMD_DATA_IO_PORT 0xCD7
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#define AMD_SMBUS_BASE_REG 0x2C
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#define AMD_PM_INDEX 0x00
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/* nVidia-Specific constants */
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#define NV_SMBUS_ADR_REG 0x20
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#define NV_OLD_SMBUS_ADR_REG 0x50
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#define NVSMBCNT smbusbase + 0
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#define NVSMBSTS smbusbase + 1
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#define NVSMBADD smbusbase + 2
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#define NVSMBCMD smbusbase + 3
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#define NVSMBDAT(x) (smbusbase + 4 + (x))
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#define NVSMBCNT_WRITE 0x00
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#define NVSMBCNT_READ 0x01
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#define NVSMBCNT_QUICK 0x02
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#define NVSMBCNT_BYTE 0x04
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#define NVSMBCNT_BYTE_DATA 0x06
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#define NVSMBCNT_WORD_DATA 0x08
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#define NVSMBSTS_DONE 0x80
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#define NVSMBSTS_ALRM 0x40
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#define NVSMBSTS_RES 0x20
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#define NVSMBSTS_STATUS 0x1f
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struct pci_smbus_controller {
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unsigned vendor;
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unsigned device;
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void (*get_adr)(void);
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};
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typedef struct spd_infos {
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bool isValid;
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uint8_t slot_num;
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uint16_t jedec_code;
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uint32_t module_size;
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char *type;
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uint8_t sku[32];
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uint8_t sku_len;
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uint8_t XMP;
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uint16_t freq;
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bool hasECC;
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uint8_t fab_year;
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uint8_t fab_week;
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uint16_t tCL;
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uint16_t tRCD;
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uint16_t tRP;
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uint16_t tRAS;
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uint16_t tRC;
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} spd_info;
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typedef struct ram_infos {
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uint16_t freq;
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uint16_t tCL;
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uint16_t tRCD;
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uint16_t tRP;
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uint16_t tRAS;
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char *type;
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} ram_info;
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extern ram_info ram;
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/**
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* Print SMBUS Info
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*/
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void print_smbus_startup_info(void);
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#endif // SMBUS_H
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