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Sam Demeulemeester
eaeaff181b
Two per-CPU streams alternate NT-store bursts of a fresh PRSG sequence with read-verify of the previous round, forcing write-to-read turnarounds and row conflicts; odd rounds insert idle gaps to provoke PMIC load steps. Targets DDR5-era interface faults (link SI, marginal XMP/EXPO training, voltage droop) that on-die ECC cannot correct Moving PRSG vector kernels from mov_inv_rng.C to a shared module in tests/