mirror of
https://github.com/memtest86plus/memtest86plus.git
synced 2026-08-08 12:08:03 -05:00
Dongyan Qian
07d84f4f34
* loongarch: adjust 2K/3B6000M DDR rate factor * loongarch: Supports fewer cache layers than L3 For example: 2K2000 chip does not have L3, but has L2. If L2Cache is not flushed to memory, it will cause read and write data errors after cache_off.
153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef CACHE_H
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#define CACHE_H
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/**
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* \file
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*
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* Provides functions to enable, disable, and flush the CPU caches.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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*/
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#ifdef __loongarch_lp64
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#include <larchintrin.h>
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#include "string.h"
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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"cacop %0, %1\n" \
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: \
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: "i" (op), "ZC" (*(unsigned char *)(addr)))
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static inline void cache_flush(void);
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#endif
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/**
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* Disable the CPU caches.
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*/
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static inline void cache_off(void)
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{
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#if defined(__x86_64__)
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__asm__ __volatile__ ("\t"
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"movq %%cr0, %%rax \n\t"
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"orl $0x40000000, %%eax \n\t" /* Set CD */
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"movq %%rax, %%cr0 \n\t"
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"wbinvd \n"
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: /* no outputs */
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: /* no inputs */
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: "rax", "memory"
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);
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#elif defined(__i386__)
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__asm__ __volatile__ ("\t"
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"movl %%cr0, %%eax \n\t"
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"orl $0x40000000, %%eax \n\t" /* Set CD */
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"movl %%eax, %%cr0 \n\t"
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"wbinvd \n"
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: /* no outputs */
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: /* no inputs */
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: "eax", "memory"
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);
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#elif defined(__loongarch_lp64)
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cache_flush();
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__csrxchg_d(0, 3 << 4, 0x181);
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#endif
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}
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/**
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* Enable the CPU caches.
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*/
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static inline void cache_on(void)
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{
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#if defined(__x86_64__)
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__asm__ __volatile__ ("\t"
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"movq %%cr0, %%rax \n\t"
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"andl $0x9fffffff, %%eax \n\t" /* Clear CD and NW */
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"movq %%rax, %%cr0 \n"
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: /* no outputs */
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: /* no inputs */
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: "rax", "memory"
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);
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#elif defined(__i386__)
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__asm__ __volatile__ ("\t"
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"movl %%cr0, %%eax \n\t"
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"andl $0x9fffffff, %%eax \n\t" /* Clear CD and NW */
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"movl %%eax, %%cr0 \n"
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: /* no outputs */
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: /* no inputs */
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: "eax", "memory"
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);
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#elif defined(__loongarch_lp64)
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cache_flush();
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__csrxchg_d(1 << 4, 3 << 4, 0x181);
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#endif
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}
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/**
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* Flush the CPU caches.
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*/
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static inline void cache_flush(void)
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{
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#if defined(__i386__) || defined(__x86_64__)
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__asm__ __volatile__ ("\t"
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"wbinvd\n"
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: /* no outputs */
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: /* no inputs */
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: "memory"
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);
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#elif defined (__loongarch_lp64)
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uint64_t cache_present, cache_info_reg;
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/*detect_max_cache_level*/
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if (__cpucfg(0x10) & (1 << 10)) {
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cache_present = 3; //L3 unified cache
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} else if (__cpucfg(0x10) & (1 << 3)) {
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cache_present = 2; //L2 unified cache
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} else if (__cpucfg(0x10) & (1 << 0)) {
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cache_present = 1; //L1 data cache
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} else {
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return; //No Cache present
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}
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cache_info_reg = 0x11 + cache_present; //cache last leaf
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uint64_t ways = (__cpucfg(cache_info_reg) & 0xFFFF) + 1;
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uint64_t sets = 1 << ((__cpucfg(cache_info_reg) >> 16) & 0xFF);
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uint64_t line_size = 1 << ((__cpucfg(cache_info_reg) >> 24) & 0x7F);
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uint64_t va, i, j;
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uint64_t cpu_module[1];
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va = 0;
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cpu_module[0] = (uint64_t)__iocsrrd_d(0x20);
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if (strstr((const char *)cpu_module, "3A6000")) {
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uint8_t old_sc_cfg;
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old_sc_cfg = __iocsrrd_b(0x280);
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__iocsrwr_b(0x1, 0x280);
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for (i = 0; i < (ways * 3); i++) {
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for (j = 0; j < sets; j++) {
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*(volatile uint32_t *)va;
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va += line_size;
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}
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}
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__iocsrwr_b(old_sc_cfg, 0x280);
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} else {
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for (i = 0; i < sets; i++) {
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for (j = 0; j < ways; j++) {
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switch (cache_present) {
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case 1:
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cache_op(0x9,va); //Flush L1
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break;
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case 2:
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cache_op(0xA,va); //Flush L2
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break;
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case 3:
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cache_op(0xB,va); //Flush L3
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break;
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}
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va++;
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}
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va -= ways;
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va += line_size;
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}
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}
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#endif
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}
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#endif // CACHE_H
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