Renamed UDQInput -> UDQCOnfig
UDQConfig object has merged DEFINE & ASSIGN Log use of UDA for output purposes Output UDQ keywords to restart file Add size() method to UDQConfig Add UDQVarTYpe member to UDQInput class Add UDQIndex type to keep track of sequence number of variable types Add unit to UDQInput class use maps Add operator[] to UDQConfig class Use UDQInput class when creating restart file UDQInput: use correct input index Add UDQActive::get() method Make sure UDQ DEFINE overwrite correctly WIP WIP - further code to output IGPH vector WIP Fix IUAD input index Output use_index for IUAD Fix bug with size of IUAD array UAD usage hashing based on udqstring and controltype Add UDQ test and input file Refactor UDQActive - handles vanishing UDA minor correction for iuad[1] and for test_UDQ_x.cpp Further work for making unit tests for UDQ restart data WIP Further work unit tests WIP some minor corrections WIP changes to add first version of BOOST test for IUDQ WIP Added code to write InteHead and DoubHead data as well as IGPH to restart file, Further added unit tests to the writing of UDQ data add code to output IUAP array Fixed group-group2 transition, disable Restart output WIP Initial changes to add DUDW array to restart output WIP further work on DUDW data WIP - further work to output and test DUDW vector data to restart file Further changes to write DUDW array to Restartfile
This commit is contained in:
Joakim Hove
committed by
Jostein Alvestad
Jostein Alvestad
parent
f2bc961bd4
commit
16a8f4040c
@@ -24,7 +24,7 @@ EQLDIMS
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2 /
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WELLDIMS
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4 20 4 2 /
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5 20 4 2 /
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UNIFIN
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UNIFOUT
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@@ -336,10 +336,10 @@ UDQ
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DEFINE WUOPRL (WOPR PROD1 - 150) * 0.90 /
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DEFINE WULPRL (WLPR PROD1 - 200) * 0.90 /
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DEFINE WUOPRU (WOPR PROD2 - 250) * 0.80 /
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DEFINE GUOPRU (GOPR WGRP2 - 449) * 0.77 /
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DEFINE GUOPRU (GOPR GRP1 - 449) * 0.77 /
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DEFINE WULPRU (WLPR PROD2 - 300) * 0.80 /
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ASSIGN WULPRL 400. /
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DEFINE FULPR (FLPR - 543) * 0.65 /
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DEFINE FULPR (FLPR - 543) * 0.65 /
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DEFINE WUOPRL (WOPR PROD1 - 170) * 0.60 /
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-- units
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UNITS WUOPRL SM3/DAY /
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@@ -347,7 +347,7 @@ UNITS WULPRL SM3/DAY /
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UNITS GUOPRU SM3/DAY /
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UNITS WUOPRU SM3/DAY /
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UNITS WULPRU SM3/DAY /
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UNITS FULPR SM3/DAY /
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UNITS FULPR SM3/DAY /
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--
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/
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@@ -1240,6 +1240,7 @@ UDQ
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BOOST_CHECK( fuopr.is<UDQDefine>() );
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const auto& def2 = fuopr.get<UDQDefine>();
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BOOST_CHECK_EQUAL(def2.input_string(), "MAX(WOPR)");
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}
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@@ -1370,6 +1371,208 @@ WCONPROD
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)";
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auto schedule = make_udq_schedule(udq_string);
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// First timestep
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{
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const auto& udq_active = schedule.udqActive(0);
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BOOST_CHECK(udq_active);
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BOOST_CHECK_EQUAL(udq_active.IUAD_size(), 2);
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const auto& record0 = udq_active[0];
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BOOST_CHECK_EQUAL( record0.uad_code, 300004);
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BOOST_CHECK_EQUAL( record0.input_index, 2);
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BOOST_CHECK_EQUAL( record0.use_count, 2);
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BOOST_CHECK_EQUAL( record0.use_index, 0);
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const auto& record1 = udq_active[1];
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BOOST_CHECK_EQUAL( record1.uad_code, 600004);
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BOOST_CHECK_EQUAL( record1.input_index, 3);
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BOOST_CHECK_EQUAL( record1.use_count, 2);
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BOOST_CHECK_EQUAL( record1.use_index, 2);
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}
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{
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// Second timestep
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// - The WUOPRU and WULPRU udq are still used in the same manner for the PROD1 well.
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// - The new UDQs WUXO and WUXL are now used for the PROD2 well.
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const auto& udq_active = schedule.udqActive(1);
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BOOST_CHECK(udq_active);
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BOOST_CHECK_EQUAL(udq_active.IUAD_size(), 4);
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const auto& record0 = udq_active[0];
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BOOST_CHECK_EQUAL( record0.uad_code, 300004);
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BOOST_CHECK_EQUAL( record0.input_index, 2);
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BOOST_CHECK_EQUAL( record0.use_count, 1);
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BOOST_CHECK_EQUAL( record0.use_index, 0);
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const auto& record1 = udq_active[1];
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BOOST_CHECK_EQUAL( record1.uad_code, 600004);
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BOOST_CHECK_EQUAL( record1.input_index, 3);
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BOOST_CHECK_EQUAL( record1.use_count, 1);
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BOOST_CHECK_EQUAL( record1.use_index, 1);
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const auto& record2 = udq_active[2];
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BOOST_CHECK_EQUAL( record2.uad_code, 300004);
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BOOST_CHECK_EQUAL( record2.input_index, 4);
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BOOST_CHECK_EQUAL( record2.use_count, 1);
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BOOST_CHECK_EQUAL( record2.use_index, 2);
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const auto& record3 = udq_active[3];
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BOOST_CHECK_EQUAL( record3.uad_code, 600004);
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BOOST_CHECK_EQUAL( record3.input_index, 5);
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BOOST_CHECK_EQUAL( record3.use_count, 1);
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BOOST_CHECK_EQUAL( record3.use_index, 3);
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}
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{
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// Third timestep
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// - The new UDQs WUXO and WUXL are now used for the PROD2 well.
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// - The PROD1 well does not use UDQ
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const auto& udq_active = schedule.udqActive(2);
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BOOST_CHECK(udq_active);
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BOOST_CHECK_EQUAL(udq_active.IUAD_size(), 2);
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const auto& record0 = udq_active[0];
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BOOST_CHECK_EQUAL( record0.uad_code, 300004);
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BOOST_CHECK_EQUAL( record0.input_index, 4);
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BOOST_CHECK_EQUAL( record0.use_count, 1);
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BOOST_CHECK_EQUAL( record0.use_index, 0);
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const auto& record1 = udq_active[1];
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BOOST_CHECK_EQUAL( record1.uad_code, 600004);
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BOOST_CHECK_EQUAL( record1.input_index, 5);
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BOOST_CHECK_EQUAL( record1.use_count, 1);
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BOOST_CHECK_EQUAL( record1.use_index, 1);
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BOOST_AUTO_TEST_CASE(UDQ_USAGE) {
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UDQActive usage;
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UDQParams params;
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UDQConfig conf(params);
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BOOST_CHECK_EQUAL( usage.IUAD_size(), 0 );
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UDAValue uda1("WUX");
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conf.add_assign(uda1.get<std::string>(), {}, 100);
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usage.update(conf, uda1, "W1", UDAControl::WCONPROD_ORAT);
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BOOST_CHECK_EQUAL( usage.IUAD_size(), 1 );
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BOOST_CHECK_EQUAL( usage[0].use_count, 1);
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usage.update(conf, uda1, "W1", UDAControl::WCONPROD_GRAT);
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BOOST_CHECK_EQUAL( usage.IUAD_size(), 2 );
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BOOST_CHECK_EQUAL( usage[1].use_count, 1);
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const auto& rec = usage[0];
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BOOST_CHECK_EQUAL(rec.wgname, "W1");
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BOOST_CHECK_EQUAL(rec.udq, "WUX");
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BOOST_CHECK(rec.control == UDAControl::WCONPROD_ORAT);
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for (std::size_t index = 0; index < usage.IUAD_size(); index++) {
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const auto& record = usage[index];
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BOOST_CHECK_EQUAL(record.input_index, 0);
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BOOST_CHECK_EQUAL(record.wgname, "W1");
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if (index == 0)
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BOOST_CHECK(record.control == UDAControl::WCONPROD_ORAT);
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else
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BOOST_CHECK(record.control == UDAControl::WCONPROD_GRAT);
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index += 1;
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}
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}
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BOOST_AUTO_TEST_CASE(IntegrationTest) {
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#include "data/integration_tests/udq.data"
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auto schedule = make_schedule(deck_string);
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{
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const auto& active = schedule.udqActive(1);
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BOOST_CHECK_EQUAL(active.IUAD_size(), 4);
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BOOST_CHECK(active[0].control == UDAControl::WCONPROD_ORAT);
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BOOST_CHECK(active[1].control == UDAControl::WCONPROD_LRAT);
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BOOST_CHECK(active[2].control == UDAControl::WCONPROD_ORAT);
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BOOST_CHECK(active[3].control == UDAControl::WCONPROD_LRAT);
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BOOST_CHECK(active[0].wgname == "OPL02");
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BOOST_CHECK(active[1].wgname == "OPL02");
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BOOST_CHECK(active[2].wgname == "OPU02");
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BOOST_CHECK(active[3].wgname == "OPU02");
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BOOST_CHECK(active[0].udq == "WUOPRL");
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BOOST_CHECK(active[1].udq == "WULPRL");
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BOOST_CHECK(active[2].udq == "WUOPRU");
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BOOST_CHECK(active[3].udq == "WULPRU");
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BOOST_CHECK(active[0].input_index == 0);
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BOOST_CHECK(active[1].input_index == 1);
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BOOST_CHECK(active[2].input_index == 2);
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BOOST_CHECK(active[3].input_index == 3);
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BOOST_CHECK(active[0].use_count == 1);
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BOOST_CHECK(active[1].use_count == 1);
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BOOST_CHECK(active[2].use_count == 1);
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BOOST_CHECK(active[3].use_count == 1);
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}
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}
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Schedule make_udq_schedule(const std::string& schedule_string) {
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#include "data/integration_tests/udq2.data"
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deck_string += schedule_string;
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return make_schedule(deck_string);
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}
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BOOST_AUTO_TEST_CASE(IntegrationTest2) {
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const std::string udq_string = R"(
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UDQ
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DEFINE WUOPRL (WOPR PROD1 - 150) * 0.90 /
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DEFINE WULPRL (WLPR PROD1 - 200) * 0.90 /
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DEFINE WUOPRU (WOPR PROD2 - 250) * 0.80 /
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DEFINE WULPRU (WLPR PROD2 - 300) * 0.80 /
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DEFINE WUOPRL (WOPR PROD1 - 170) * 0.60 /
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DEFINE WUXO (WOPR PROD1 - 170) * 0.60 /
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DEFINE WUXL (WOPR PROD1 - 170) * 0.60 /
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-- units
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UNITS WUOPRL SM3/DAY /
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UNITS WULPRL SM3/DAY /
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UNITS WUOPRU SM3/DAY /
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UNITS WULPRU SM3/DAY /
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/
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WCONPROD
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'PROD1' 'OPEN' 'GRUP' WUOPRU 1* 1* WULPRU 1* 60.0 / single wells
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/
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WCONPROD
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'PROD2' 'OPEN' 'GRUP' WUOPRU 1* 1* WULPRU 1* 60.0 / single wells
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/
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WCONINJE
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'WINJ1' 'WAT' 'OPEN' 'BHP' 1* 1200 3500 1* /
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'WINJ2' 'WAT' 'OPEN' 'BHP' 1* 800 3500 1* /
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/
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TSTEP
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5 /
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WCONPROD
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'PROD2' 'OPEN' 'GRUP' WUXO 1* 1* WUXL 1* 60.0 / single wells
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/
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TSTEP
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5 /
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WCONPROD
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'PROD1' 'OPEN' 'GRUP' 100 1* 1* 100 1* 60.0 / single wells
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/
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)";
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auto schedule = make_udq_schedule(udq_string);
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@@ -40,7 +40,7 @@ namespace {
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Opm::Deck first_sim(std::string fname) {
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return Opm::Parser{}.parseFile(fname);
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}
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/*
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Opm::UDQActive udq_active() {
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int update_count = 0;
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// construct record data for udq_active
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@@ -67,8 +67,41 @@ namespace {
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}
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return udq_act;
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}
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*/
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}
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Opm::SummaryState sum_state()
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{
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auto state = Opm::SummaryState{};
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state.update_well_var("PROD1", "WUOPRL", 210.);
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state.update_well_var("PROD2", "WUOPRL", 211.);
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state.update_well_var("WINJ1", "WUOPRL", 212.);
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state.update_well_var("WINJ2", "WUOPRL", 213.);
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state.update_well_var("PROD1", "WULPRL", 230.);
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state.update_well_var("PROD2", "WULPRL", 231.);
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state.update_well_var("WINJ1", "WULPRL", 232.);
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state.update_well_var("WINJ2", "WULPRL", 233.);
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state.update_well_var("PROD1", "WUOPRU", 220.);
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state.update_well_var("PROD2", "WUOPRU", 221.);
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state.update_well_var("WINJ1", "WUOPRU", 222.);
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state.update_well_var("WINJ2", "WUOPRU", 223.);
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state.update_group_var("WGRP1", "GUOPRU", 360.);
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state.update_group_var("WGRP2", "GUOPRU", 361.);
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state.update_group_var("GRP1", "GUOPRU", 362.);
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state.update_group_var("GRP2", "GUOPRU", 363.);
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state.update_well_var("PROD1", "WULPRU", 160.);
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state.update_well_var("PROD2", "WULPRU", 161.);
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state.update_well_var("WINJ1", "WULPRU", 162.);
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state.update_well_var("WINJ2", "WULPRU", 163.);
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state.update("FULPR", 460.);
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return state;
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}
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//int main(int argc, char* argv[])
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@@ -76,8 +109,8 @@ struct SimulationCase
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{
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explicit SimulationCase(const Opm::Deck& deck)
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: es { deck }
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, grid { deck }
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, sched{ deck, es }
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, grid { deck }
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, sched{ deck, es }
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{}
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// Order requirement: 'es' must be declared/initialised before 'sched'.
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@@ -97,11 +130,11 @@ BOOST_AUTO_TEST_CASE (Declared_UDQ_data)
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const auto simCase = SimulationCase{first_sim("UDQ_TEST_WCONPROD_IUAD-2.DATA")};
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Opm::EclipseState es = simCase.es;
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Opm::SummaryState st = sum_state();
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Opm::Schedule sched = simCase.sched;
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Opm::EclipseGrid grid = simCase.grid;
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const auto& ioConfig = es.getIOConfig();
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const auto& restart = es.cfg().restart();
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//Opm::UDQActive udq_act = udq_active();
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//const auto& restart = es.cfg().restart();
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// Report Step 1: 2008-10-10 --> 2011-01-20
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const auto rptStep = std::size_t{1};
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@@ -112,9 +145,9 @@ BOOST_AUTO_TEST_CASE (Declared_UDQ_data)
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Opm::EclIO::OutputStream::ResultSet { outputDir, baseName },
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rptStep,
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Opm::EclIO::OutputStream::Formatted { ioConfig.getFMTOUT() },
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Opm::EclIO::OutputStream::Unified { ioConfig.getUNIFOUT() }
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Opm::EclIO::OutputStream::Unified { ioConfig.getUNIFOUT() }
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};
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double secs_elapsed = 3.1536E07;
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const auto ih = Opm::RestartIO::Helpers::createInteHead(es, grid, sched,
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secs_elapsed, rptStep, rptStep);
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@@ -125,14 +158,15 @@ BOOST_AUTO_TEST_CASE (Declared_UDQ_data)
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const auto udqDims = Opm::RestartIO::Helpers::createUdqDims(sched, rptStep, ih);
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auto udqData = Opm::RestartIO::Helpers::AggregateUDQData(udqDims);
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udqData.captureDeclaredUDQData(sched, rptStep, ih);
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udqData.captureDeclaredUDQData(sched, rptStep, st, ih);
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rstFile.write("IUDQ", udqData.getIUDQ());
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rstFile.write("IUAD", udqData.getIUAD());
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rstFile.write("IGPH", udqData.getIGPH());
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rstFile.write("IUAP", udqData.getIUAP());
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rstFile.write("ZUDN", udqData.getZUDN());
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rstFile.write("ZUDL", udqData.getZUDL());
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rstFile.write("IUDQ", udqData.getIUDQ());
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rstFile.write("DUDW", udqData.getDUDW());
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rstFile.write("IUAD", udqData.getIUAD());
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rstFile.write("IUAP", udqData.getIUAP());
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rstFile.write("IGPH", udqData.getIGPH());
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{
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/*
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@@ -327,19 +361,18 @@ BOOST_AUTO_TEST_CASE (Declared_UDQ_data)
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BOOST_CHECK_EQUAL(zUdl[start + 2].c_str() , "0) * 0.6"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 3].c_str() , "0 "); // udq NO. 1
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/*start = 1*udqDims[5];
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BOOST_CHECK_EQUAL(zUdl[start + 0].c_str() , "(WLPR PR"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 1].c_str() , "OD1 - 20"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 2].c_str() , "0) * 0.9"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 3].c_str() , "0 "); // udq NO. 1
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*/
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start = 3*udqDims[5];
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BOOST_CHECK_EQUAL(zUdl[start + 0].c_str() , "(GOPR WG"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 1].c_str() , "RP2 - 44"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 2].c_str() , "9) * 0.7"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 3].c_str() , "7 "); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 0].c_str() , "(GOPR GR"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 1].c_str() , "P1 - 449"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 2].c_str() , ") * 0.77"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 3].c_str() , " "); // udq NO. 1
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start = 4*udqDims[5];
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BOOST_CHECK_EQUAL(zUdl[start + 0].c_str() , "(WLPR PR"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 1].c_str() , "OD2 - 30"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 2].c_str() , "0) * 0.8"); // udq NO. 1
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BOOST_CHECK_EQUAL(zUdl[start + 3].c_str() , "0 "); // udq NO. 1
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start = 5*udqDims[5];
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BOOST_CHECK_EQUAL(zUdl[start + 0].c_str() , "(FLPR - "); // udq NO. 1
|
||||
BOOST_CHECK_EQUAL(zUdl[start + 1].c_str() , "543) * 0"); // udq NO. 1
|
||||
@@ -348,6 +381,34 @@ BOOST_AUTO_TEST_CASE (Declared_UDQ_data)
|
||||
|
||||
}
|
||||
|
||||
|
||||
{
|
||||
/*
|
||||
'DUDW ' 24 'DOUB'
|
||||
|
||||
Dimension = max no wells * no of UDQ's
|
||||
Value = value of UDQ for the different wells
|
||||
*/
|
||||
|
||||
const auto& dUdw = udqData.getDUDW();
|
||||
|
||||
auto start = 0*udqDims[8];
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 0] , 210); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 1] , 211); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 2] , 212); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 3] , 213); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 4] , -0.3E+21); // duDw NO. 1
|
||||
|
||||
start = 1*udqDims[8];
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 0] , 230); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 1] , 231); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 2] , 232); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 3] , 233); // duDw NO. 1
|
||||
BOOST_CHECK_EQUAL(dUdw[start + 4] , -0.3E+21); // duDw NO. 1
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user