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[CPU] Fixed block layout tails process on SSE for MVN impl (#21534)

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Chenhu Wang authored and GitHub committed 2023-12-12 11:52:11 +01:00
1 parent b31aad78b0
commit 14639d292d
2 files changed
+46 -14
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src/plugins/intel_cpu/src/nodes/mvn.cpp
+14 -14
View File
@@ -605,6 +605,7 @@ private:
// cover vector and tails on avx512, avx2
// cover on sse, 2 part vector, first part vector and second part tails, first part tails
Xbyak::Label label_exit;
for (int i = 0; i < repeats; i++) {
if (i > 0) {
reset_with_offset(4);
@@ -621,12 +622,6 @@ private:
L(label_tails);
{
if (i > 0) {
// empty second half on sse
cmp(reg_rt_shape, 0);
jbe(label_end);
}
Xbyak::Label label_sse_full_size;
if (isa == cpu::x64::sse41) {
// on sse, first 4 could be done with vector manner
@@ -635,17 +630,22 @@ private:
}
worker_tails_unroll();
jmp(label_end, T_NEAR);
// exit directly if tails is done, for all platforms
jmp(label_exit, T_NEAR);
L(label_sse_full_size);
{
worker_vector_unroll();
save_result();
sub(reg_rt_shape, 4);
// exit directly if empty second half
cmp(reg_rt_shape, 0);
jbe(label_exit, T_NEAR);
}
}
L(label_end);
}
L(label_exit);
}
inline void worker_vector_unroll() {
@@ -1098,6 +1098,7 @@ private:
// cover vector and tails on avx512, avx2
// cover on sse, 2 part vector, first part vector and second part tails, first part tails
Xbyak::Label label_exit;
int repeats = (isa == cpu::x64::sse41) ? 2 : 1;
for (int i = 0; i < repeats; i++) {
if (i > 0) {
@@ -1114,12 +1115,6 @@ private:
L(label_tails);
{
if (i > 0) {
// empty second half on sse
cmp(reg_rt_shape, 0);
jbe(label_end);
}
Xbyak::Label label_sse_full_size;
if (isa == cpu::x64::sse41) {
// on sse, first 4 could be done with vector manner
@@ -1128,16 +1123,21 @@ private:
}
worker_tails_unroll();
jmp(label_end, T_NEAR);
// exit directly if tails is done, for all platforms
jmp(label_exit, T_NEAR);
L(label_sse_full_size);
{
worker_mvn_vector_unroll(reg_work_amount);
sub(reg_rt_shape, 4);
// exit directly if empty second half
cmp(reg_rt_shape, 0);
jbe(label_exit, T_NEAR);
}
}
L(label_end);
}
L(label_exit);
}
// nspc norm per channel with unroll
src/plugins/intel_cpu/tests/functional/single_layer_tests/instances/x64/mvn.cpp
+32
View File
@@ -175,6 +175,38 @@ const auto Mvn4DStatic = ::testing::Combine(
INSTANTIATE_TEST_SUITE_P(smoke_CompareWithRefs_Mvn4D_Static, MvnLayerCPUTest, Mvn4DStatic, MvnLayerCPUTest::getTestCaseName);
// test cases of tails process of block layout with f32 precision.
// could cover SSE41 code path on SSE41 platform(currrent bf16 cases are skipped on non-avx512 machine)
const std::vector<ov::Shape>& inputShapesStatic_4D_CTails() {
static const std::vector<ov::Shape> inputShapesStatic_4D = {
{1, 3, 2, 2},
{1, 4, 5, 5},
{1, 7, 2, 5},
};
return inputShapesStatic_4D;
}
ov::AnyMap additionalConfigCTails = {
{ov::hint::inference_precision.name(), ov::element::f32}
};
const auto Mvn4DStaticCTails = ::testing::Combine(
::testing::Combine(
::testing::ValuesIn(static_shapes_to_test_representation(inputShapesStatic_4D_CTails())),
::testing::Values(ElementType::f32),
::testing::ValuesIn(emptyReductionAxes()),
::testing::Values(false),
::testing::ValuesIn(normalizeVariance),
::testing::ValuesIn(epsilon())),
::testing::ValuesIn(filterCPUSpecificParams(cpuParams_4D)),
::testing::Values(emptyFusingSpec),
::testing::Values(ElementType::f32),
::testing::Values(ElementType::f32),
::testing::Values(additionalConfigCTails));
INSTANTIATE_TEST_SUITE_P(CompareWithRefs_Mvn4D_Static_CTails, MvnLayerCPUTest, Mvn4DStaticCTails, MvnLayerCPUTest::getTestCaseName);
// end
const auto Mvn5DStatic = ::testing::Combine(
::testing::Combine(
::testing::ValuesIn(static_shapes_to_test_representation(inputShapesStatic_5D())),