[GPU] remove WA for fallback pooling to cldnn. (#13540)

* remove WA for fallback pooling to cldnn.
* remove unnecessary code for deconv
* add format::bfzyx/b_fs_zyx_fsv32 to reduction_onednn

src/plugins/intel_gpu/src/graph/impls/onednn/reduction_onednn.cpp

@@ -106,12 +106,18 @@ attach_reduction_onednn::attach_reduction_onednn() {
     };
     std::vector<format::type> fmt = {
         format::bfyx,
+        format::bfzyx,
         format::b_fs_yx_fsv16,
         format::b_fs_yx_fsv32,
+        format::b_fs_zyx_fsv32,
         format::bs_fs_yx_bsv16_fsv16,
         format::bs_fs_yx_bsv16_fsv32,
         format::bs_fs_yx_bsv32_fsv16,
         format::bs_fs_yx_bsv32_fsv32,
+        format::bs_fs_zyx_bsv16_fsv16,
+        format::bs_fs_zyx_bsv16_fsv32,
+        format::bs_fs_zyx_bsv32_fsv16,
+        format::bs_fs_zyx_bsv32_fsv32,
     };
 
     implementation_map<reduce>::add(impl_types::onednn, reduction_onednn::create, dt, fmt);

src/plugins/intel_gpu/src/graph/layout_optimizer.cpp

@@ -785,9 +785,6 @@ static bool is_node_for_onednn(reduce_node const& node, format preferred_format)
     }
 
     auto input_layout = input.get_output_layout();
-    if (input_layout.get_partial_shape().size() > 4) {
-        return false;
-    }
 
     // redundant reduce is not acceptable on oneDNN reduction
     if (node.get_output_layout() == input_layout) {
@@ -816,7 +813,6 @@ static bool is_node_for_onednn(deconvolution_node const& node) {
     if (input_layout.is_dynamic() || output_layout.is_dynamic())
         return false;
 
-    // Onednn deconv does not support cross-precision
     bool onednn_valid_dt = layout_optimizer::are_data_types_suitable_for_onednn((program_node&)node);
 
     bool onednn_valid_params = onednn_valid_dt &&
@@ -1128,7 +1124,6 @@ layout layout_optimizer::get_expected_layout(layout const& current_layout,
     auto expected_data_type = current_layout.data_type;
     auto expected_format = current_layout.format;
     bool use_onednn_impls = _optimization_attributes.use_onednn_impls;
-    const auto& device_info = node.get_program().get_engine().get_device_info();
 
     if (use_onednn_impls && is_node_for_onednn(node)) {
         // XXX: need to take the situation into consideration where it is called from prepare_primitive_fusing
@@ -1140,7 +1135,7 @@ layout layout_optimizer::get_expected_layout(layout const& current_layout,
             expected_format = cldnn::format::bs_fs_zyx_bsv16_fsv16;
         else
             expected_format = cldnn::format::b_fs_zyx_fsv16;
-    } else if ((_optimization_attributes.b_fs_yx_fsv16_network || device_info.supports_immad) &&
+    } else if ((_optimization_attributes.b_fs_yx_fsv16_network) &&
                deconvolution_b_fs_yx_fsv16_opt(current_layout, output_or_weights_layout, prim)) {
         auto input_tensor = node.get_dependency(0).get_output_layout().get_tensor();
         int input_features = input_tensor.feature[0];
@@ -1469,16 +1464,6 @@ impl_types layout_optimizer::get_preferred_impl_type(program_node& node, format
             impl_candidate = impl_types::ocl;
         }
 
-        // WA: fallback cldnn if onednn pooling's layout is b_fs_zyx_fsv32 and i8.
-        if (node.is_type<pooling>()) {
-            auto pool_layout = node.get_output_layout();
-            if (pool_layout.data_type == data_types::i8) {
-                if (pool_layout.format == format::b_fs_zyx_fsv32 || pool_layout.format == format::bs_fs_zyx_bsv16_fsv32 ||
-                    pool_layout.format == format::bs_fs_zyx_bsv32_fsv32)
-                    impl_candidate = impl_types::ocl;
-            }
-        }
-
         if (node.is_type<deconvolution>()) {
             if (!is_node_for_onednn(node.as<deconvolution>()))
                 impl_candidate = impl_types::ocl;

src/plugins/intel_gpu/src/plugin/transformations/convert_pooling_to_reduce.cpp

@@ -28,7 +28,7 @@ ov::intel_gpu::ConvertAvgPoolingToReduce::ConvertAvgPoolingToReduce() {
         int64_t rank = pool->get_input_partial_shape(0).size();
         auto input_shape = pool->get_input_shape(0);
         // Check if input spatial size is same with kernel size.
-        bool has_same_spatial_size = rank > 2 && std::equal(input_shape.begin() + 2, input_shape.end(), kernel.begin());
+        bool has_same_spatial_size = rank > 2 && std::equal(input_shape.end() - (rank - 2), input_shape.end(), kernel.end() - (rank - 2));
         // Check if pads are zeros.
         bool no_padding =
             std::count(pads_begin.begin(), pads_begin.end(), 0) == static_cast<int64_t>(pads_begin.size()) &&