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[CPU] proofreading correction (#17246)

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This commit is contained in:
Chenhu Wang
2023-04-28 18:13:30 +08:00
committed by GitHub
parent 740ee3c185
commit 43842e2486
2 changed files with 4 additions and 4 deletions
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2
src/plugins/intel_cpu/src/nodes/interpolate.cpp
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@@ -1779,7 +1779,7 @@ public:
port_mask = PortMask(Interpolate::SIZE_OR_SCALE_ID_V11, Interpolate::AXES_ID_V11);
} else {
IE_THROW() << "Shape infer factory cannot be created for " << m_op->get_type_name() << " node with name: " << m_op->get_friendly_name()
<<", only version 4 and 11 is supported.";
<<", only versions 4 and 11 are supported.";
}
return std::make_shared<NgraphShapeInfer>(make_shape_inference(m_op), port_mask);
}

6
src/plugins/intel_cpu/src/nodes/interpolate.h
View File

@@ -103,9 +103,9 @@ public:
private:
bool is_version11 = true;
InterpolateAttrs interpAttrs;
// Some FEs or preprocessing step resize spatial dimenion for tensor with NHWC layout memory,
// but imported as planar layout[abcd] with axis[1,2] for convinence. In this case, for pillow modes and no pad for now,
// nhwc layout pass and kernel can be used for this planar layout and axis settings(NCHWAsNHWC is true) to get higher perf with
// Some FEs or preprocessing step resize spatial dimension for tensor with NHWC layout memory,
// but imported as planar layout[abcd] with axis[1,2] for convenience. In this case, for pillow modes without pad for now,
// nhwc layout path and the kernel(nhwc layout executor) can be used for this planar layout and axis settings(NCHWAsNHWC is true) to get higher perf with
// 1. logical shape alignment [abcd-nhwc] to [adbc-nchw].
// 2. axis alignment [1,2] to [2,3].
// 3. config planar layout support and treated it as channel_first layout.