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ARM32 ACL kernels in oneDNN (#17142)

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* ARM32 ACL kernels in oneDNN

* Fixed review comments

* Fixed ERF

* Disabled several eltwise tests on arm32
This commit is contained in:
Ilya Lavrenov
2023-04-26 13:50:10 +04:00
committed by GitHub
parent 02bfa7804b
commit da91b33763
6 changed files with 113 additions and 102 deletions
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2
src/plugins/intel_cpu/CMakeLists.txt
View File

@@ -43,7 +43,7 @@ endif()
add_definitions(-DOV_CPU_WITH_DNNL)
set(OV_CPU_WITH_DNNL ON)
if(DNNL_AARCH64_USE_ACL)
if(DNNL_USE_ACL)
add_definitions(-DOV_CPU_WITH_ACL)
set(OV_CPU_WITH_ACL ON)
endif()

104
src/plugins/intel_cpu/src/nodes/executors/acl/acl_eltwise.cpp
View File

@@ -26,6 +26,110 @@ inline VectorDims reshape_sizes(VectorDims dims) {
return result_dims;
}
bool AclEltwiseExecutorBuilder::isSupported(const EltwiseAttrs& eltwiseAttrs,
const std::vector<MemoryDescPtr>& srcDescs,
const std::vector<MemoryDescPtr>& dstDescs) const {
auto checkPrecision = [&srcDescs, &dstDescs](std::vector<Precision> srcVecPrc, Precision dstPrc) -> bool {
for (int i = 0; i < srcDescs.size(); i++) {
if (srcDescs[i]->getPrecision() != srcVecPrc[i]) return false;
}
if (dstDescs[0]->getPrecision() != dstPrc) { return false; }
return true;
};
switch (eltwiseAttrs.algorithm) {
case Algorithm::EltwiseSqrt:
case Algorithm::EltwiseDivide:
case Algorithm::EltwiseRelu:
#ifdef OPENVINO_ARCH_ARM64
case Algorithm::EltwiseGeluErf:
#endif
case Algorithm::EltwiseElu:
case Algorithm::EltwiseTanh:
case Algorithm::EltwiseSigmoid:
// case Algorithm::EltwisePowerDynamic: // TODO: ACL version doesn't work https://github.com/ARM-software/ComputeLibrary/issues/1047
case Algorithm::EltwiseSoftRelu:
case Algorithm::EltwiseClamp:
//case Algorithm::EltwiseSwish: // TODO: efficientdet-d0 accuracy drops if ACL Swish is used
case Algorithm::EltwisePrelu:
case Algorithm::EltwiseHswish:
if (!(checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseAbs:
case Algorithm::EltwiseExp:
case Algorithm::EltwiseLog:
if (!(checkPrecision({Precision::I32, Precision::I32}, Precision::I32) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseMaximum:
case Algorithm::EltwiseMinimum:
case Algorithm::EltwiseSquaredDifference:
if (!(checkPrecision({Precision::I16, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::I32, Precision::I32}, Precision::I32) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseAdd:
case Algorithm::EltwiseSubtract:
if (!(checkPrecision({Precision::U8, Precision::U8}, Precision::U8) ||
checkPrecision({Precision::I16, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::I32, Precision::I32}, Precision::I32) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseMultiply:
if (!(checkPrecision({Precision::U8, Precision::U8}, Precision::U8) ||
checkPrecision({Precision::U8, Precision::U8}, Precision::I16) ||
checkPrecision({Precision::U8, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::I16, Precision::U8}, Precision::I16) ||
checkPrecision({Precision::I16, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
// ACL supports only U8 precision on output for comparison operations
case Algorithm::EltwiseEqual:
case Algorithm::EltwiseNotEqual:
case Algorithm::EltwiseGreater:
case Algorithm::EltwiseGreaterEqual:
case Algorithm::EltwiseLess:
case Algorithm::EltwiseLessEqual:
if (!(checkPrecision({Precision::U8, Precision::U8}, Precision::U8) ||
checkPrecision({Precision::I16, Precision::I16}, Precision::U8) ||
checkPrecision({Precision::I32, Precision::I32}, Precision::U8) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::U8) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::U8))) {
return false;
}
break;
default:
return false;
}
for (const auto & srcDesc : srcDescs) {
if (getAclDataLayoutByMemoryDesc(srcDesc) == arm_compute::DataLayout::UNKNOWN)
return false;
}
for (const auto & dstDesc : dstDescs) {
if (getAclDataLayoutByMemoryDesc(dstDesc) == arm_compute::DataLayout::UNKNOWN)
return false;
}
return true;
}
AclEltwiseExecutor::AclEltwiseExecutor(const ExecutorContext::CPtr context) : EltwiseExecutor(context) {}
bool AclEltwiseExecutor::init(const EltwiseAttrs &eltwiseAttrs, const std::vector<MemoryDescPtr> &srcDescs,

99
src/plugins/intel_cpu/src/nodes/executors/acl/acl_eltwise.hpp
View File

@@ -40,104 +40,7 @@ class AclEltwiseExecutorBuilder : public EltwiseExecutorBuilder {
public:
bool isSupported(const EltwiseAttrs& eltwiseAttrs,
const std::vector<MemoryDescPtr>& srcDescs,
const std::vector<MemoryDescPtr>& dstDescs) const override {
auto checkPrecision = [&srcDescs, &dstDescs](std::vector<Precision> srcVecPrc, Precision dstPrc) -> bool {
for (int i = 0; i < srcDescs.size(); i++) {
if (srcDescs[i]->getPrecision() != srcVecPrc[i]) return false;
}
if (dstDescs[0]->getPrecision() != dstPrc) { return false; }
return true;
};
switch (eltwiseAttrs.algorithm) {
case Algorithm::EltwiseSqrt:
case Algorithm::EltwiseDivide:
case Algorithm::EltwiseRelu:
case Algorithm::EltwiseGeluErf:
case Algorithm::EltwiseElu:
case Algorithm::EltwiseTanh:
case Algorithm::EltwiseSigmoid:
// case Algorithm::EltwisePowerDynamic: // TODO: ACL version doesn't work https://github.com/ARM-software/ComputeLibrary/issues/1047
case Algorithm::EltwiseSoftRelu:
case Algorithm::EltwiseClamp:
//case Algorithm::EltwiseSwish: // TODO: efficientdet-d0 accuracy drops if ACL Swish is used
case Algorithm::EltwisePrelu:
case Algorithm::EltwiseHswish:
if (!(checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseAbs:
case Algorithm::EltwiseExp:
case Algorithm::EltwiseLog:
if (!(checkPrecision({Precision::I32, Precision::I32}, Precision::I32) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseMaximum:
case Algorithm::EltwiseMinimum:
case Algorithm::EltwiseSquaredDifference:
if (!(checkPrecision({Precision::I16, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::I32, Precision::I32}, Precision::I32) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseAdd:
case Algorithm::EltwiseSubtract:
if (!(checkPrecision({Precision::U8, Precision::U8}, Precision::U8) ||
checkPrecision({Precision::I16, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::I32, Precision::I32}, Precision::I32) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
case Algorithm::EltwiseMultiply:
if (!(checkPrecision({Precision::U8, Precision::U8}, Precision::U8) ||
checkPrecision({Precision::U8, Precision::U8}, Precision::I16) ||
checkPrecision({Precision::U8, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::I16, Precision::U8}, Precision::I16) ||
checkPrecision({Precision::I16, Precision::I16}, Precision::I16) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::FP16) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::FP32))) {
return false;
}
break;
// ACL supports only U8 precision on output for comparison operations
case Algorithm::EltwiseEqual:
case Algorithm::EltwiseNotEqual:
case Algorithm::EltwiseGreater:
case Algorithm::EltwiseGreaterEqual:
case Algorithm::EltwiseLess:
case Algorithm::EltwiseLessEqual:
if (!(checkPrecision({Precision::U8, Precision::U8}, Precision::U8) ||
checkPrecision({Precision::I16, Precision::I16}, Precision::U8) ||
checkPrecision({Precision::I32, Precision::I32}, Precision::U8) ||
checkPrecision({Precision::FP16, Precision::FP16}, Precision::U8) ||
checkPrecision({Precision::FP32, Precision::FP32}, Precision::U8))) {
return false;
}
break;
default:
return false;
}
for (const auto & srcDesc : srcDescs) {
if (getAclDataLayoutByMemoryDesc(srcDesc) == arm_compute::DataLayout::UNKNOWN)
return false;
}
for (const auto & dstDesc : dstDescs) {
if (getAclDataLayoutByMemoryDesc(dstDesc) == arm_compute::DataLayout::UNKNOWN)
return false;
}
return true;
}
const std::vector<MemoryDescPtr>& dstDescs) const override;
EltwiseExecutorPtr makeExecutor(const ExecutorContext::CPtr context) const override {
return std::make_shared<AclEltwiseExecutor>(context);

5
src/plugins/intel_cpu/tests/functional/shared_tests_instances/skip_tests_config.cpp
View File

@@ -194,6 +194,11 @@ std::vector<std::string> disabledTestPatterns() {
retVector.emplace_back(R"(smoke_Quantized.*)");
#endif
#if defined(OPENVINO_ARCH_ARM)
// TODO: rounding errors
retVector.emplace_back(R"(.*iv_secondaryInputType=PARAMETER_opType=VECTOR_NetType=i32.*)");
#endif
#if !defined(OPENVINO_ARCH_X86_64)
// very time-consuming test
retVector.emplace_back(R"(.*OVInferConsistencyTest.*)");

3
src/plugins/intel_cpu/thirdparty/CMakeLists.txt vendored
View File

@@ -60,15 +60,14 @@ function(ie_add_onednn)
endif()
set(ARM_COMPUTE_SCONS_JOBS "8" CACHE STRING "Number of parallel threads to build ARM Compute Library")
set(DNNL_USE_ACL ON CACHE BOOL "" FORCE)
if(ARM)
set(DNNL_TARGET_ARCH "ARM" CACHE STRING "" FORCE)
set(DNNL_AARCH64_USE_ACL OFF CACHE BOOL "" FORCE)
set(ARM_COMPUTE_TARGET_ARCH_DEFAULT armv7a)
set(ARM_COMPUTE_TARGET_ARCHS armv7a armv7a-hf)
else()
set(DNNL_TARGET_ARCH "AARCH64" CACHE STRING "" FORCE)
set(DNNL_AARCH64_USE_ACL ON CACHE BOOL "" FORCE)
# move to separate ACL cmake
if(APPLE)
# Apple M1 / M2 is assumed

2
src/plugins/intel_cpu/thirdparty/onednn vendored

Submodule src/plugins/intel_cpu/thirdparty/onednn updated: 9b547e7cb6...e879365821