* update spec Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * use RTTI macro Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * fix op scope typo Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * simplify evaluate template function Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * override validate_and_infer_types() to align with spec Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * Add visitor API test Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * Add type_prop test Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * Add SLT asinh test in cpu/gpu plugin Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * change `T` in the spec to *T* Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * refector spec according to Cos Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * Support element type of integral Signed-off-by: Li, Tingqian <tingqian.li@intel.com> * Add new cpp files into CMakeLists.txt Signed-off-by: Li, Tingqian <tingqian.li@intel.com>
47 lines
1.0 KiB
Markdown
47 lines
1.0 KiB
Markdown
## Asinh <a name="Asinh"></a> {#openvino_docs_ops_arithmetic_Asinh_3}
|
|
|
|
**Versioned name**: *Asinh-3*
|
|
|
|
**Category**: Arithmetic unary operation
|
|
|
|
**Short description**: *Asinh* performs element-wise inverse hyperbolic sine operation (arcsinh) on a given input tensor.
|
|
|
|
**Detailed description**: *Asinh* performs element-wise inverse hyperbolic sine operation on a given input tensor, based on the following mathematical formula:
|
|
|
|
\f[
|
|
a_{i} = asinh(a_{i})
|
|
\f]
|
|
|
|
**Attributes**: *Asinh* operation has no attributes.
|
|
|
|
**Inputs**
|
|
|
|
* **1**: A tensor of type *T* and arbitrary shape. **Required.**
|
|
|
|
**Outputs**
|
|
|
|
* **1**: The result of element-wise *Asinh* operation. A tensor of type *T* and the same shape as input tensor.
|
|
|
|
**Types**
|
|
|
|
* *T*: any numeric type.
|
|
|
|
**Example**
|
|
|
|
```xml
|
|
<layer ... type="Asinh">
|
|
<input>
|
|
<port id="0">
|
|
<dim>256</dim>
|
|
<dim>56</dim>
|
|
</port>
|
|
</input>
|
|
<output>
|
|
<port id="1">
|
|
<dim>256</dim>
|
|
<dim>56</dim>
|
|
</port>
|
|
</output>
|
|
</layer>
|
|
```
|