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capabilities: Also report L2 caches

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Since some systems support control for L2 caches as well as L3 caches it
would be useful to report their configuration in capabilities.

Signed-off-by: Martin Kletzander <mkletzan@redhat.com>
Reviewed-by: Michal Privoznik <mprivozn@redhat.com>
This commit is contained in:
Martin Kletzander committed 2024-09-13 12:55:39 +02:00
1 parent 4437a775dc
commit bc97a2c043
6 files changed
+53 -1
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src/conf/capabilities.c
+1 -1
View File
@@ -2161,7 +2161,7 @@ virCapabilitiesInitCaches(virCaps *caps)
/* Minimum level to expose in capabilities. Can be lowered or removed (with
* the appropriate code below), but should not be increased, because we'd
* lose information. */
const int cache_min_level = 3;
const int cache_min_level = 2;
if (virCapabilitiesInitResctrl(caps) < 0)
return -1;
tests/vircaps2xmldata/vircaps-x86_64-caches.xml
+4
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@@ -30,6 +30,10 @@
</cells>
</topology>
<cache>
<bank id='0' level='2' type='both' size='256' unit='KiB' cpus='0-1'/>
<bank id='1' level='2' type='both' size='256' unit='KiB' cpus='2-3'/>
<bank id='2' level='2' type='both' size='256' unit='KiB' cpus='4-5'/>
<bank id='3' level='2' type='both' size='256' unit='KiB' cpus='6-7'/>
<bank id='0' level='3' type='both' size='8' unit='MiB' cpus='0-7'/>
</cache>
</host>
tests/vircaps2xmldata/vircaps-x86_64-resctrl-cdp.xml
+12
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@@ -42,6 +42,18 @@
</cells>
</topology>
<cache>
<bank id='0' level='2' type='both' size='256' unit='KiB' cpus='0'/>
<bank id='1' level='2' type='both' size='256' unit='KiB' cpus='1'/>
<bank id='2' level='2' type='both' size='256' unit='KiB' cpus='2'/>
<bank id='3' level='2' type='both' size='256' unit='KiB' cpus='3'/>
<bank id='4' level='2' type='both' size='256' unit='KiB' cpus='4'/>
<bank id='5' level='2' type='both' size='256' unit='KiB' cpus='5'/>
<bank id='8' level='2' type='both' size='256' unit='KiB' cpus='6'/>
<bank id='9' level='2' type='both' size='256' unit='KiB' cpus='7'/>
<bank id='10' level='2' type='both' size='256' unit='KiB' cpus='8'/>
<bank id='11' level='2' type='both' size='256' unit='KiB' cpus='9'/>
<bank id='12' level='2' type='both' size='256' unit='KiB' cpus='10'/>
<bank id='13' level='2' type='both' size='256' unit='KiB' cpus='11'/>
<bank id='0' level='3' type='both' size='15' unit='MiB' cpus='0-5'>
<control granularity='768' unit='KiB' type='code' maxAllocs='8'/>
<control granularity='768' unit='KiB' type='data' maxAllocs='8'/>
tests/vircaps2xmldata/vircaps-x86_64-resctrl-cmt.xml
+12
View File
@@ -42,6 +42,18 @@
</cells>
</topology>
<cache>
<bank id='0' level='2' type='both' size='256' unit='KiB' cpus='0'/>
<bank id='1' level='2' type='both' size='256' unit='KiB' cpus='1'/>
<bank id='2' level='2' type='both' size='256' unit='KiB' cpus='2'/>
<bank id='3' level='2' type='both' size='256' unit='KiB' cpus='3'/>
<bank id='4' level='2' type='both' size='256' unit='KiB' cpus='4'/>
<bank id='5' level='2' type='both' size='256' unit='KiB' cpus='5'/>
<bank id='8' level='2' type='both' size='256' unit='KiB' cpus='6'/>
<bank id='9' level='2' type='both' size='256' unit='KiB' cpus='7'/>
<bank id='10' level='2' type='both' size='256' unit='KiB' cpus='8'/>
<bank id='11' level='2' type='both' size='256' unit='KiB' cpus='9'/>
<bank id='12' level='2' type='both' size='256' unit='KiB' cpus='10'/>
<bank id='13' level='2' type='both' size='256' unit='KiB' cpus='11'/>
<bank id='0' level='3' type='both' size='15' unit='MiB' cpus='0-5'/>
<bank id='1' level='3' type='both' size='15' unit='MiB' cpus='6-11'/>
<monitor level='3' reuseThreshold='270336' maxMonitors='176'>
tests/vircaps2xmldata/vircaps-x86_64-resctrl-fake-feature.xml
+12
View File
@@ -42,6 +42,18 @@
</cells>
</topology>
<cache>
<bank id='0' level='2' type='both' size='256' unit='KiB' cpus='0'/>
<bank id='1' level='2' type='both' size='256' unit='KiB' cpus='1'/>
<bank id='2' level='2' type='both' size='256' unit='KiB' cpus='2'/>
<bank id='3' level='2' type='both' size='256' unit='KiB' cpus='3'/>
<bank id='4' level='2' type='both' size='256' unit='KiB' cpus='4'/>
<bank id='5' level='2' type='both' size='256' unit='KiB' cpus='5'/>
<bank id='8' level='2' type='both' size='256' unit='KiB' cpus='6'/>
<bank id='9' level='2' type='both' size='256' unit='KiB' cpus='7'/>
<bank id='10' level='2' type='both' size='256' unit='KiB' cpus='8'/>
<bank id='11' level='2' type='both' size='256' unit='KiB' cpus='9'/>
<bank id='12' level='2' type='both' size='256' unit='KiB' cpus='10'/>
<bank id='13' level='2' type='both' size='256' unit='KiB' cpus='11'/>
<bank id='0' level='3' type='both' size='15' unit='MiB' cpus='0-5'>
<control granularity='768' min='1536' unit='KiB' type='both' maxAllocs='4'/>
</bank>
tests/vircaps2xmldata/vircaps-x86_64-resctrl.xml
+12
View File
@@ -42,6 +42,18 @@
</cells>
</topology>
<cache>
<bank id='0' level='2' type='both' size='256' unit='KiB' cpus='0'/>
<bank id='1' level='2' type='both' size='256' unit='KiB' cpus='1'/>
<bank id='2' level='2' type='both' size='256' unit='KiB' cpus='2'/>
<bank id='3' level='2' type='both' size='256' unit='KiB' cpus='3'/>
<bank id='4' level='2' type='both' size='256' unit='KiB' cpus='4'/>
<bank id='5' level='2' type='both' size='256' unit='KiB' cpus='5'/>
<bank id='8' level='2' type='both' size='256' unit='KiB' cpus='6'/>
<bank id='9' level='2' type='both' size='256' unit='KiB' cpus='7'/>
<bank id='10' level='2' type='both' size='256' unit='KiB' cpus='8'/>
<bank id='11' level='2' type='both' size='256' unit='KiB' cpus='9'/>
<bank id='12' level='2' type='both' size='256' unit='KiB' cpus='10'/>
<bank id='13' level='2' type='both' size='256' unit='KiB' cpus='11'/>
<bank id='0' level='3' type='both' size='15' unit='MiB' cpus='0-5'>
<control granularity='768' min='1536' unit='KiB' type='both' maxAllocs='4'/>
</bank>