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memtest86plus/app/config.h

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Initial commit.
2020-05-24 15:30:55 -05:00
// SPDX-License-Identifier: GPL-2.0
#ifndef CONFIG_H
#define CONFIG_H
Add ability to generate internal API documentation using Doxygen.
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/**
* \file
*
Initial commit.
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* Provides the configuration settings and pop-up menu.
*
Exclude copyright notices from Doxygen file descriptions.
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*//*
Remove distinction between physical and virtual CPUs. This is no longer needed, now we can display as many CPUs as we can physically handle.
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* Copyright (C) 2020-2022 Martin Whitaker.
Initial commit.
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*/
#include <stdbool.h>
#include <stdint.h>
#include "smp.h"
Add AP Enumeration to distinguish P-Core from E-Core on Hybrid CPUs (#62) Add AP Enumeration to distinguish E-Core from P-Core on Intel Hybrid CPUs, and exclude them from the selected cores by default. Including E-Cores slows down some tests and takes longer to catch memory errors. A new exclude_ecores flag has been added in config.c to include E-Cores if needed.
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#include "cpuid.h"
Initial commit.
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typedef enum {
PAR,
SEQ,
ONE
} cpu_mode_t;
typedef enum {
ERROR_MODE_NONE,
ERROR_MODE_SUMMARY,
ERROR_MODE_ADDRESS,
ERROR_MODE_BADRAM
} error_mode_t;
Faster barrier implementation. The old barrier implementation was very slow when running on a multi-socket machine (pcmemtest issue 16). The new implementation provides two options: - when blocked, spin on a thread-local flag - when blocked, execute a HLT instruction and wait for a NMI The first option might be faster, but we need to measure it to find out. A new boot command line option is provided to select between the two, with a third setting that uses a mixture of the two.
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typedef enum {
POWER_SAVE_OFF,
POWER_SAVE_LOW,
POWER_SAVE_HIGH
} power_save_t;
Initial commit.
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extern uintptr_t pm_limit_lower;
extern uintptr_t pm_limit_upper;
extern uintptr_t num_pages_to_test;
extern cpu_mode_t cpu_mode;
extern error_mode_t error_mode;
Remove distinction between physical and virtual CPUs. This is no longer needed, now we can display as many CPUs as we can physically handle.
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extern cpu_state_t cpu_state[MAX_CPUS];
Initial commit.
2020-05-24 15:30:55 -05:00
Add AP Enumeration to distinguish P-Core from E-Core on Hybrid CPUs (#62) Add AP Enumeration to distinguish E-Core from P-Core on Intel Hybrid CPUs, and exclude them from the selected cores by default. Including E-Cores slows down some tests and takes longer to catch memory errors. A new exclude_ecores flag has been added in config.c to include E-Cores if needed.
2022-07-16 06:28:53 -05:00
extern core_type_t hybrid_core_type[MAX_CPUS];
extern bool exclude_ecores;
Rework Line #7 left block. Add preliminary CPUID function to detect CPU Topology
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extern bool smp_enabled;
Add a command line option to disable the big PASS/FAIL status display. (#227)
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extern bool enable_big_status;
Initial commit.
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extern bool enable_temperature;
extern bool enable_trace;
Early SMBUS functions (#2) & EFI Reset (#17)
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extern bool enable_sm;
Add support for Serial/TTY (#32) * Add preliminary support for TTY Serial/UART (#15) * Use shadow_buffer instead of VGA buffer to get a framebuffer-agnostic TTY supprot * Added menu browsing & inputs from Serial TTY (#15) * Add fix for degree symbol on TTY. Correct serial.c & serial.h file created with CRLF (#15) * Move tty_error_redraw() to insure correct redraw when a error occurs * Many reindent / cleanup * Various optimization from @martinwhitaker comments
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extern bool enable_tty;
Separate benchmark from smbus/smbios and add a separate flag to enable/disable it
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extern bool enable_bench;
Add Memory Controller Registers polling to get current DRAM Timings/Frequency (#306) Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
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extern bool enable_mch_read;
Early SMBUS functions (#2) & EFI Reset (#17)
2022-03-13 23:35:36 -05:00
Add support for boot command line options.
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extern bool pause_at_start;
Faster barrier implementation. The old barrier implementation was very slow when running on a multi-socket machine (pcmemtest issue 16). The new implementation provides two options: - when blocked, spin on a thread-local flag - when blocked, execute a HLT instruction and wait for a NMI The first option might be faster, but we need to measure it to find out. A new boot command line option is provided to select between the two, with a third setting that uses a mixture of the two.
2022-02-28 14:21:50 -06:00
extern power_save_t power_save;
Add support for Serial/TTY (#32) * Add preliminary support for TTY Serial/UART (#15) * Use shadow_buffer instead of VGA buffer to get a framebuffer-agnostic TTY supprot * Added menu browsing & inputs from Serial TTY (#15) * Add fix for degree symbol on TTY. Correct serial.c & serial.h file created with CRLF (#15) * Move tty_error_redraw() to insure correct redraw when a error occurs * Many reindent / cleanup * Various optimization from @martinwhitaker comments
2022-04-04 11:31:54 -05:00
extern int tty_params_port;
extern int tty_params_baud;
extern int tty_update_period;
Add 'press any key to remove' message on banner By default, don't re-display FAIL banner after it has been discarded (#130 & #173) Add an option to re-display FAIL banner even if previously discarded
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extern bool err_banner_redraw;
Initial commit.
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void config_init(void);
void config_menu(bool initial);
void initial_config(void);
#endif // CONFIG_H
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