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https://github.com/memtest86plus/memtest86plus.git
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7aeac7271f
Read the memory controller configuration (instead of just relying on SPD data) to get the actual live settings. Currently supported platforms: * Intel SNB to RPL (Core 2nd Gen to Core 13th Gen) - Desktop only (no Server nor Mobile) * AMD SMR to RPL (Zen to Zen4) - Desktop only (no Server, Mobile nor APU). Individual commits below for archival: * First functions skeleton for reading IMC/ECC Registers * Change directory name from 'chipsets' to 'mch' (Memory Controller Hub) * Add Intel HSW and fix new files encoding * First Intel HSW IMC implementation * Add an option to disable MCH registers polling * Remove old include from Makefiles * Better Makefile and padding fixes * Statically init 'imc' struct to generate string relocation record * Small typos & code fixes * Add IMC support for Intel Core 6/7/8/9th Gen (SKL/KBL/CFL/CML) This is a bit more complex than Haswell and below because MMIO switched to 64-bit with Skylake (lot of) betatesting needed * Add IMC read support for Intel SNB/IVB (2nd/3rd gen Core) * Fix hard-lock on Intel SNB/IVB due to wrong access type on MCHBAR pointer * Move AMD SMN Registers & offsets to a specific header file * Add IMC Read support for AMD Zen/Zen2 CPUs * Change 'IMC' to 'MCH' in Makefiles to match actual mch/ directory * Add IMC Reading support for Intel ADL&RPL CPUs (Core Gen12&13) * Add support for Intel Rocket Lake (Core 11th Gen) and AMD Vermeer * Add IMC reading for AMD Zen4 'Raphael' AM5 CPUs * Various Cleanup #1 Change terminology from Intel-based 'MCH' (Memory Controller Hub) to more universal 'IMC' (Integrated Memory Controller) Integrate imc_type var into imc struct. Remove previously created AMD SNM header file * Various Cleanup 2 * Change DDR5 display format for IMC specs DDR5 Freq can be > 10000 and timings up to 63-127-127-127, which overwflow the available space. This commit remove the raw frequency on DDR5 (which may be incorrect due to Gear mechanism) and leave a bit of space to display the Gear engaged in the future
80 lines
1.4 KiB
C
80 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#ifndef CONFIG_H
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#define CONFIG_H
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/**
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* \file
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*
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* Provides the configuration settings and pop-up menu.
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*
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*//*
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* Copyright (C) 2020-2022 Martin Whitaker.
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "smp.h"
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#include "cpuid.h"
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typedef enum {
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PAR,
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SEQ,
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ONE
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} cpu_mode_t;
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typedef enum {
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ERROR_MODE_NONE,
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ERROR_MODE_SUMMARY,
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ERROR_MODE_ADDRESS,
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ERROR_MODE_BADRAM
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} error_mode_t;
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typedef enum {
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POWER_SAVE_OFF,
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POWER_SAVE_LOW,
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POWER_SAVE_HIGH
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} power_save_t;
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extern uintptr_t pm_limit_lower;
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extern uintptr_t pm_limit_upper;
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extern uintptr_t num_pages_to_test;
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extern cpu_mode_t cpu_mode;
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extern error_mode_t error_mode;
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extern cpu_state_t cpu_state[MAX_CPUS];
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extern core_type_t hybrid_core_type[MAX_CPUS];
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extern bool exclude_ecores;
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extern bool smp_enabled;
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extern bool enable_big_status;
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extern bool enable_temperature;
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extern bool enable_trace;
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extern bool enable_sm;
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extern bool enable_tty;
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extern bool enable_bench;
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extern bool enable_mch_read;
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extern bool pause_at_start;
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extern power_save_t power_save;
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extern int tty_params_port;
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extern int tty_params_baud;
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extern int tty_update_period;
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extern bool err_banner_redraw;
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void config_init(void);
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void config_menu(bool initial);
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void initial_config(void);
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#endif // CONFIG_H
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