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Add support for Zen4/AM5 DDR5 SPD

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This commit is contained in:
Sam Demeulemeester
2022-09-09 18:09:13 +02:00
parent f265d1f1c5
commit 03a5222ee2
3 changed files with 8 additions and 5 deletions
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6
system/cpuinfo.c
View File

@@ -296,10 +296,12 @@ static void determine_imc(void)
imc_type = IMC_K18; // Hygon (Family 18h)
break;
case 0xA:
if(cpuid_info.version.extendedModel == 5) {
if (cpuid_info.version.extendedModel == 5) {
imc_type = IMC_K19_CZN; // AMD Cezanne APU (Model 0x50-5F - Family 19h)
} else if (cpuid_info.version.extendedModel >= 6) {
imc_type = IMC_K19_RPL; // Zen4 (Family 19h)
} else {
imc_type = IMC_K19; // Zen3 & Zen4 (Family 19h)
imc_type = IMC_K19; // Zen3 (Family 19h)
}
default:
break;

3
system/cpuinfo.h
View File

@@ -59,8 +59,9 @@
#define IMC_K16 0x8050 // Kabini & related (Family 16h)
#define IMC_K17 0x8060 // Zen & Zen2 (Family 17h)
#define IMC_K18 0x8070 // Hygon (Family 18h)
#define IMC_K19 0x8080 // Zen3 & Zen4(Family 19h)
#define IMC_K19 0x8080 // Zen3 (Family 19h)
#define IMC_K19_CZN 0x8081 // Cezanne APU
#define IMC_K19_RPL 0x8091 // Zen4 (Family 19h)
/**
* A string identifying the CPU make and model.

4
system/smbus.c
View File

@@ -1366,8 +1366,8 @@ static bool fch_zen_get_smb(void)
__outb(AMD_PM_INDEX, AMD_INDEX_IO_PORT);
pm_reg |= __inb(AMD_DATA_IO_PORT);
// Special case for AMD Cezanne (get smb address in memory)
if (imc_type == IMC_K19_CZN && pm_reg == 0xFFFF) {
// Special case for AMD Family 19h & Extended Model > 4 (get smb address in memory)
if ((imc_type == IMC_K19_CZN || imc_type == IMC_K19_RPL) && pm_reg == 0xFFFF) {
smbusbase = ((*(const uint32_t *)(0xFED80000 + 0x300) >> 8) & 0xFF) << 8;
return true;
}