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Add support for Intel AlderLake-N CPUs

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This commit is contained in:
Sam Demeulemeester 2023-04-24 00:29:37 +02:00
parent fa4e903509
commit 0fd2e4c37a
4 changed files with 25 additions and 2 deletions
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3
system/cpuinfo.c
View File

@ -493,6 +493,9 @@ static void determine_imc(void)
case 0x9:
imc_type = IMC_KBL; // Core 7/8/9th Gen (Kaby/Coffee/Comet Lake)
break;
case 0xB:
imc_type = IMC_ADL_N; // Core 12th Gen (Alder Lake-N - Gracemont E-Cores only)
break;
default:
break;
}

3
system/cpuinfo.h
View File

@ -8,7 +8,7 @@
*
*//*
* Copyright (C) 2020-2022 Martin Whitaker.
* Copyright (C) 2004-2022 Sam Demeulemeester.
* Copyright (C) 2004-2023 Sam Demeulemeester.
*/
#include <stdbool.h>
@ -47,6 +47,7 @@
#define IMC_KBL_UY 0x3030 // Core 7/8/9th Gen (Kaby/Coffee/Comet/Amber Lake-U/Y)
#define IMC_ICL 0x3040 // Core 10th Gen (IceLake-Y)
#define IMC_TGL 0x3050 // Core 11th Gen (Tiger Lake-U)
#define IMC_ADL_N 0x3061 // Core 12th Gen (Alder Lake-N - Gracemont E-Cores only)
#define IMC_BYT 0x4010 // Atom Bay Trail
#define IMC_CDT 0x4020 // Atom Cedar Trail

18
system/hwquirks.c
View File

@ -99,6 +99,15 @@ static void amd_k8_revfg_temp(void)
cpu_temp_offset = 21.0f;
}
static void adl_unlock_smbus(void)
{
uint16_t x = pci_config_read16(0, 31, 4, 0x04);
if (!(x & 1)) {
pci_config_write16(0, 31, 4, 0x04, x | 1);
}
}
// ---------------------
// -- Public function --
// ---------------------
@ -199,4 +208,13 @@ void quirks_init(void)
}
}
}
// --------------------------------------------------
// -- SMBus unlock for ADL-N (and probably others) --
// --------------------------------------------------
if (imc_type == IMC_ADL_N && pci_config_read16(0, 31, 4, 0x2) == 0x54A3) { // ADL-N
quirk.id = QUIRK_ADL_SMB_UNLOCK;
quirk.type |= QUIRK_TYPE_SMBUS;
quirk.process = adl_unlock_smbus;
}
}

3
system/hwquirks.h
View File

@ -28,7 +28,8 @@ typedef enum {
QUIRK_X10SDV_NOSMP,
QUIRK_K8_BSTEP_NOTEMP,
QUIRK_K8_REVFG_TEMP,
QUIRK_AMD_ERRATA_319
QUIRK_AMD_ERRATA_319,
QUIRK_ADL_SMB_UNLOCK
} quirk_id_t;
typedef struct {