Add support for Intel Lunar Lake & Panther Lake CPUs

system/cpuinfo.h

@@ -48,7 +48,9 @@
 #define IMC_KBL_UY      0x3030  // Core 7/8/9th Gen (Kaby/Coffee/Comet/Amber Lake-U/Y)
 #define IMC_ICL         0x3040  // Core 10th Gen (IceLake-Y)
 #define IMC_TGL         0x3050  // Core 11th Gen (Tiger Lake-U)
-#define IMC_ADL_N       0x3061  // Core 12th Gen (Alder Lake-N - Gracemont E-Cores only)
+#define IMC_ADL_N       0x3060  // Core 12th Gen (Alder Lake-N - Gracemont E-Cores only)
+#define IMC_LNL         0x3070  // Core Ultra 2nd Gen (Lunar Lake)
+#define IMC_PTL         0x3080  // Core Ultra 3rd Gen (Panther Lake)
 
 #define IMC_BYT         0x4010  // Atom Bay Trail
 #define IMC_SLT         0x4020  // Atom Silverthorne / Diamondville
@@ -57,6 +59,9 @@
 #define IMC_CDT         0x4050  // Atom Cedar Trail / Cedarview
 #define IMC_TNC         0x4060  // Atom Tunnel Creek / Lincroft
 
+#define IMC_NVL_S       0x5000  // Nova Lake-S
+#define IMC_NVL_H       0x5010  // Nova Lake-H
+
 #define IMC_K8          0x8000  // Old K8
 #define IMC_K10         0x8010  // K10 (Family 10h & 11h)
 #define IMC_K12         0x8020  // A-Series APU (Family 12h)

system/x86/cpuinfo.c

@@ -502,6 +502,9 @@ static void determine_imc(void)
               case 0x8:
                 imc.family = IMC_TGL;         // Core 11th Gen (Tiger Lake-U)
                 break;
+              case 0xC:
+                imc.family = IMC_PTL;         // Core Ultra Serie 3 (Panther Lake)
+                break;
               default:
                 break;
             }
@@ -518,6 +521,9 @@ static void determine_imc(void)
               case 0x8:
                 imc.family = IMC_TGL;         // Core 11th Gen (Tiger Lake-Y)
                 break;
+              case 0xB:
+                imc.family = IMC_LNL;         // Core Ultra Serie 2 (Lunar Lake)
+                break;
               default:
                 break;
             }
@@ -578,6 +584,29 @@ static void determine_imc(void)
         }
         return;
     }
+
+    // Check Intel IMC (Next Gen CPUID)
+    if (cpuid_info.vendor_id.str[0] == 'G' && cpuid_info.version.family == 15 && cpuid_info.version.extendedFamily)
+    {
+        switch (cpuid_info.version.extendedFamily) {
+            case 0x3:
+              switch (cpuid_info.version.model) {
+                case 0x1:
+                  imc.family = IMC_NVL_S;      // Nova Lake-S
+                  break;
+                case 0x3:
+                  imc.family = IMC_NVL_H;      // Nova Lake-Hx
+                  break;
+                default:
+                  break;
+              }
+
+            default:
+              break;
+        }
+        return;
+    }
+
 }
 
 static void determine_cpu_model(void)

system/x86/i2c.c

@@ -183,7 +183,7 @@ static const uint16_t intel_ich5_dids[] =
     //0x5796,  // Birch Stream (SOC)
     0x7722,  // Arrow Lake-H (SOC)
     //0xA822,  // Lunar Lake
-    //0xE322,  // Panther Lake-H (SOC)
+    0xE322,  // Panther Lake-H (SOC)
     //0xE422,  // Panther Lake-P (SOC)
 };
 

system/x86/memctrl.c

@@ -62,6 +62,8 @@ void memctrl_init(void)
         break;
       case IMC_ARL:
       case IMC_MTL:
+      case IMC_LNL:
+      case IMC_PTL:
         get_imc_config_intel_mtl();
       default:
         break;