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Fix SiS 530 & ALi Aladdin IV/V motherboard cache detection

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Adds external L2 cache size detection for Socket 7 boards with SiS 530
  northbridge, and extends the existing ALi quirk to also cover Aladdin IV
  (M1531) in addition to Aladdin V (M1541).

  Tested on: K6-II + SiS 530 with 512KB L2 cache.

  Closes #602
  Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
This commit is contained in:
Nikolaos Barkas
2026-05-17 19:56:29 +02:00
committed by Sam Demeulemeester
parent f9a30b0fa6
commit d3827673d7
2 changed files with 55 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files
system/hwquirks.c
+53 -13
View File
@@ -60,9 +60,10 @@ static int *get_motherboard_cache(void)
return NULL;
}
static void get_m1541_l2_cache_size(void)
static void get_m1531_41_mb_cache_size(void)
{
if (l2_cache != 0) {
int *const mb_cache = get_motherboard_cache();
if (!mb_cache) {
return;
}
@@ -71,12 +72,40 @@ static void get_m1541_l2_cache_size(void)
return;
}
// Get L2 Cache Size with L2CC-1 Register[3:2]
uint8_t reg = (pci_config_read8(0, 0, 0, 0x41) >> 2) & 3;
// Get L2 Cache Size from L2CC-1 Register (bits differ per chip variant)
uint8_t ali_reg = pci_config_read8(0, 0, 0, 0x41);
if (reg == 0b00) { l2_cache = 256; }
if (reg == 0b01) { l2_cache = 512; }
if (reg == 0b10) { l2_cache = 1024; }
if (quirk.root_did == 0x1531) { // ALi Aladdin IV (M1531): Register[2:1]
switch ((ali_reg >> 1) & 0x3) {
case 0b01: *mb_cache = 256; break;
case 0b10: *mb_cache = 512; break;
case 0b11: *mb_cache = 1024; break;
}
} else { // ALi Aladdin V (M1541): Register[3:2]
switch ((ali_reg >> 2) & 0x3) {
case 0b00: *mb_cache = 256; break;
case 0b01: *mb_cache = 512; break;
case 0b10: *mb_cache = 1024; break;
}
}
}
static void get_sis_530_mb_cache_size(void)
{
int *const mb_cache = get_motherboard_cache();
if (!mb_cache) {
return;
}
uint8_t sis_reg = pci_config_read8(0, 0, 0, 0x51);
// Check if cache is enabled with Register[7]
if ((sis_reg & 0x80) == 0) {
return;
}
// Get cache size with Register[5:4]
*mb_cache = 256 << ((sis_reg >> 4) & 0x03);
}
static void get_vt82c585_597_mb_cache_size(void)
@@ -187,15 +216,16 @@ void quirks_init(void)
quirk.root_did = pci_config_read16(0, 0, 0, PCI_DID_REG);
quirk.process = NULL;
// -------------------------
// -- ALi Aladdin V Quirk --
// -------------------------
// -------------------------------------------------
// -- ALi Aladdin IV (M1531) & V (M1541) Quirks --
// -------------------------------------------------
// As on many Socket 7 Motherboards, the L2 cache is external and must
// be detected by a proprietary way based on chipset registers
if (quirk.root_vid == PCI_VID_ALI && quirk.root_did == 0x1541) { // ALi Aladdin V (M1541)
quirk.id = QUIRK_ALI_ALADDIN_V;
if (quirk.root_vid == PCI_VID_ALI && (quirk.root_did == 0x1531 // ALi Aladdin IV (M1531)
|| quirk.root_did == 0x1541)) { // ALi Aladdin V (M1541)
quirk.id = QUIRK_ALI_ALADDIN_IV_V;
quirk.type |= QUIRK_TYPE_MEM_SIZE;
quirk.process = get_m1541_l2_cache_size;
quirk.process = get_m1531_41_mb_cache_size;
}
// -------------------------------------------------------------------
@@ -209,6 +239,16 @@ void quirks_init(void)
quirk.process = get_vt82c585_597_mb_cache_size;
}
// --------------------------
// -- SiS 530 Quirk --
// --------------------------
// Motherboard cache detection
else if (quirk.root_vid == PCI_VID_SIS && quirk.root_did == 0x0530) { // SiS 530
quirk.id = QUIRK_SIS_530;
quirk.type |= QUIRK_TYPE_MEM_SIZE;
quirk.process = get_sis_530_mb_cache_size;
}
// ------------------------
// -- ASUS TUSL2-C Quirk --
// ------------------------
system/hwquirks.h
+2 -1
View File
@@ -24,12 +24,13 @@
typedef enum {
QUIRK_NONE,
QUIRK_TUSL2,
QUIRK_ALI_ALADDIN_V,
QUIRK_ALI_ALADDIN_IV_V,
QUIRK_X10SDV_NOSMP,
QUIRK_K8_BSTEP_NOTEMP,
QUIRK_K8_REVFG_TEMP,
QUIRK_AMD_ERRATA_319,
QUIRK_VIA_VP,
QUIRK_SIS_530,
QUIRK_LOONGSON7A00_EHCI_WORKARD,
QUIRK_UNHIDE_ICH05,
QUIRK_UNHIDE_ASUS_SMBUS,