* Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs
Use extended CPUID for VIA C3/C7/Nano cache information.
Use MSR reads for Nano/Zhaoxin and VIA C7 processor temperature.
Tested on VIA C7-D 1.5GHz.
* Small code conventions fixes
* Fix overallocation of cpuid_cache_info_t union (From PR #263)
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Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
Some CPU like Intel Yorkfield (Core 2 Quad) reports max CPUID > 0xB but doesn't support CPUID = 0xB. Check x2apic flag to be sure CPUID 0xB is supported. If not, fallback to older detection method
Add AP Enumeration to distinguish E-Core from P-Core on Intel Hybrid CPUs, and exclude them from the selected cores by default. Including E-Cores slows down some tests and takes longer to catch memory errors.
A new exclude_ecores flag has been added in config.c to include E-Cores if needed.
