Commit Graph

191 Commits

Author SHA1 Message Date
Sam Demeulemeester
22663f89bb
Add support for AMD K8 temperature reporting. (#268)
Add various quirks to handle AMD temp sensors erratas
2023-02-13 22:29:17 +01:00
Sam Demeulemeester
c38b0cbc5f [SMBUS] Add support for nVidia nForce 3 2023-02-13 19:43:09 +01:00
Sam Demeulemeester
dfc41f7196 Solve incorrect core/thread count on some VIA CPUs
No Cyrix / VIA / CentaurHauls / Zhaoxin CPUs support HT, so disable it.
2023-02-11 19:00:36 +01:00
Jonathan Teh
8305d47675
Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs (#259)
* Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs

Use extended CPUID for VIA C3/C7/Nano cache information.

Use MSR reads for Nano/Zhaoxin and VIA C7 processor temperature.

Tested on VIA C7-D 1.5GHz.

* Small code conventions fixes

* Fix overallocation of cpuid_cache_info_t union (From PR #263)

---------

Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
2023-02-10 22:32:31 +01:00
Jonathan Teh
a47f681151 smbus: Add support for VIA VT8237
Tested on Jetway J7F2 with VT8237R+.

Signed-off-by: Jonathan Teh <jonathan.teh@outlook.com>
2023-02-05 08:22:13 +01:00
Sam Demeulemeester
485bfa46a3
Add a quirk to disable SMP on SuperMicro X10SDV (#244) 2023-01-30 16:47:54 +01:00
Sam Demeulemeester
b15a8bb632 Add SPD support for ATI SB400 Southbridge 2023-01-23 16:09:32 +01:00
martinwhitaker
327495ec61
Allow use on headless EFI systems. (#242)
A headless EFI system may have no GOP devices. In this case, disable
output to the physical display, but continue to write to the shadow
buffer. This allows operation via a serial console.
2023-01-23 15:50:52 +01:00
Sam Demeulemeester
10e8435604 Add SPD support for legacy VIA Southbridges (VT82C686A/B & VT8235)
(From PR #236)

Author: Corentin Labbe clabbe.montjoie@gmail.com
Co-developed-by: Lionel Debroux lionel_debroux@yahoo.fr
2023-01-23 15:01:48 +01:00
Martin Whitaker
a1af48a8cf Fix and improve documentation in heap.h (issue #232) 2023-01-03 11:55:51 +00:00
Martin Whitaker
aaa0cffaa6 Use virtual memory base address when probing USB controllers (issue #180)
We still want to display the physical address for debug purposes, but
must access the controller via the possibly remapped virtual address.
2022-10-07 13:06:42 +01:00
Martin Whitaker
66b1389348 Revert workaround for issue #6 and issue #71 (commit 3a10701).
The early USB handoff is a better fix for those issues.
2022-10-07 09:33:23 +01:00
martinwhitaker
407fb811c2
Take ownership of all USB controllers before probing for devices. (#167)
When two controllers are attached to a physical port (e.g. in the
case of EHCI and its companion controllers, problems can occur if
the BIOS still has control of one controller when we try to use the
other one. So perform a first pass to scan the PCI bus and take
ownership of and reset all the controllers we find, and perform a
second pass to initialise the controllers and probe for attached
devices.

As we don't support hot plugging, split the second pass into two,
with the first probing the EHCI controllers and handing over any
low and full speed devices to the companion controllers, and the
second probing the remaining controller types.
2022-10-07 09:32:09 +01:00
Lionel Debroux
1c4d7f4089
Document PCI vendor and device IDs for several SMBus controller models from SiS, EFAR and ALi; move the PCI vendor ID defines from system/smbus.h to system/pci.h and add several vendor IDs; use the defines from system/pci.h in system/hwquirks.c. (#154)
Inspired by #126.
2022-09-14 18:57:10 +02:00
Martin Whitaker
c41159084d Guard against unsupported or invalid USB controller types. 2022-09-09 19:48:59 +01:00
Sam Demeulemeester
03a5222ee2 Add support for Zen4/AM5 DDR5 SPD 2022-09-09 18:09:13 +02:00
Martin Whitaker
f265d1f1c5 Fix EHCI and XHCI drivers to handle USB1 hubs (issue #156) 2022-09-08 18:09:43 +01:00
Sam Demeulemeester
18f12116c0 Fix a rare capacity detection issue with DDR3 modules built using 3 or 4 ranks 2022-08-29 02:50:11 +02:00
Sam Demeulemeester
385f912776 Fix date decoding issue: week 53 is actually valid for some years 2022-08-29 02:12:05 +02:00
Sam Demeulemeester
6799bfba3c Fix timings decoding issues with DDR3 XMP Modules. Add quirks for early modules based on XMP Draft 2022-08-29 01:59:36 +02:00
01e3
540270513f smbus: introduce and use bcd_to_ui8 helper function
Introduce bcd_to_ui8 for converting BCD into uint8_t.

Currently, smbus.c is the only user of this code so I placed it there.
Once (if?) there are more, we may want to move it to a dedicated ".h" file.

Replace all BCD conversion in smbus.c with a call to bcd_to_ui8().

No change in the binary output.
2022-08-28 18:14:41 +02:00
01e3
5686da4b1d smbus: optimize parse_spd_* functions
Convert calling / return convention for all parse_spd_* functions from
returning the value of spd_info structure to updating the received
reference. This also allows to move / remove some boilerplate code,
like initializing spdi/curspd and setting slot_num.

At the end, print_smbus_startup_info wants curspd to be updated,
so we can do this in a more efficient way.

Before:
      text       data        bss      total filename
     10784       3887         18      14689 build32/system/smbus.o
     10486       4399         18      14903 build64/system/smbus.o

     79353      51101      13088     143542 build32/memtest_shared
     78438      58077     294432     430947 build64/memtest_shared

After:
      text       data        bss      total filename
     10379       3871         18      14268 build32/system/smbus.o
      9833       4399         18      14250 build64/system/smbus.o

     78937      51101      13088     143126 build32/memtest_shared
     77782      58077     294432     430291 build64/memtest_shared

gcc-11.3.0.
2022-08-28 18:14:41 +02:00
01e3
43b0f64ddb smbus: refactor SPD SKU (part number) handling
Replace SPD SKU reading code repeated multiple times across
all the parse_spd_* functions with a dedicated read_sku function.

Convert spd_infos.sku from len+data into classic NULL-terminated C-string.
Takes the same space, but simplifies handling. Also, use char instead of
uint8_t so no conversion is needed when printing.

Change the way how the end of part number is handled. Stop on the first
non-ASCII character and then trim all trailing spaces. This allows SKUs
with two (or more) spaces inside the name to be handled properly.

Finally, fix incorrect / inconsistent part number length handling, with
the following end result:
 - parse_spd_sdram: 18 [73-90] (no change)
 - parse_spd_rdram: 18 [73-90] (no change)
 - parse_spd_ddr:   18 [73-90] (no change)
 - parse_spd_ddr2:  18 [73-90] (no change)
 - parse_spd_ddr3:  20+1=21 -> 18 [128-145]
 - parse_spd_ddr4:  20+1=21 -> 20 [329-348]
 - parse_spd_ddr5:  29+1=30 -> 30 [521-550] (technicaly no change)

Before:
      text       data        bss      total filename
     13143       3795         18      16956 build32/system/smbus.o
     11735       4359         18      16112 build64/system/smbus.o

     81705      51133      13088     145926 build32/memtest_shared
     79686      58109     294432     432227 build64/memtest_shared

After:
      text       data        bss      total filename
     10784       3887         18      14689 build32/system/smbus.o
     10486       4399         18      14903 build64/system/smbus.o

     79353      51101      13088     143542 build32/memtest_shared
     78438      58077     294432     430947 build64/memtest_shared

gcc-11.3.0.
2022-08-28 18:14:41 +02:00
Sam Demeulemeester
0f8981412c
Various fixes on SPD decoding algorithms (#152)
* [DDR5] Fix rounding errors on SPD Timings

* [DDR5] Add a rounding factor of ~0.3% according to JEDEC to solve the last rounding issue found on NETAC Modules

* [DDR5] Add missing package ranks per channel parameter in total module capacity algorithm

* [DDR4] Fix rounding issues in SPD timings & frequency

* [DDR3] Fix rounding issues in SPD timings & frequency decoding. Check XMP Profile #2. Add a quirk for Kingston based on very early XMP 1.0 specs

* [DDR2] Fix CAS detection & rounding issues in SPD timings w/ EPP

* [DDR] Correct SPD timings rounding issues & add support for x.5 CAS latencies

* [SDR] Correct SPD Timings decoding due to rounding errors

* Add various JEP106 Manufacturers found while debugging

* Update timings display function to handle x.5 CAS
2022-08-26 21:56:12 +02:00
Sam Demeulemeester
02702fa8c5 Change check to be sure Extended Topology Information (CPUID.0BH:EBX[15:0]) is supported 2022-08-15 22:26:22 +02:00
a1346054
9660eead4e
Simple maintenance improvements (#145)
* Fix typos

* Add missing final newline

* Trim trailing whitespace
2022-08-15 17:51:48 +02:00
Martin Whitaker
148dfd4d54 Apply the USB_2_STEP_INIT option when using an XHCI controller.
This was added to the generic assign_address() method, but the XHCI
driver overrides that.
2022-08-05 20:48:24 +01:00
Martin Whitaker
1316c6c099 Fix scanning of an external USB hub attached to an Intel XHCI (issue #135)
The Intel controller requires unused fields in the input context to be zero.
2022-08-05 20:40:18 +01:00
Sam Demeulemeester
8a3cac8133 Fix an issue while detection Core topology on Core 2 CPU.
Some CPU like Intel Yorkfield (Core 2 Quad) reports max CPUID > 0xB but doesn't support CPUID = 0xB. Check x2apic flag to be sure CPUID 0xB is supported. If not, fallback to older detection method
2022-07-26 20:02:58 +02:00
Lionel Debroux
408fdb8db6 Switch to an array of heaps in the heap manager, and heap IDs in the allocation functions. 2022-07-25 12:53:21 +02:00
Martin Whitaker
13d9569041 By default, only enable USB keyboard detection when booted in UEFI mode.
Most legacy BIOSs will support USB legacy keyboard emulation. Using that
will avoid having to reserve memory for the USB drivers, and should
improve the chance of having a working keyboard without having to work
around various USB device quirks.
2022-07-24 13:56:41 +01:00
Sam Demeulemeester
740df34656 Remove now useless IMC check to allow temperature reporting on more older CPUs 2022-07-23 23:59:49 +02:00
Sam Demeulemeester
cf156adc4a Solve an issue with Core 2 Duo/Quad and same gen CPUs, where HTT flag is enabled in CPUID while the CPU does not support SMT. (#125 #129)
Now compare the number of physical core with the number of reserved APIC to check if SMT is really available or not
2022-07-23 23:47:06 +02:00
Sam Demeulemeester
53f61e6b87 Add 'Heoriady' and 'Golden Empire' to the list of known JEDEC Manufacturers for SPD decoding (#22) 2022-07-23 23:01:53 +02:00
Sam Demeulemeester
187bc8609e Add support for nForce 410/430 & 680a/680i/780i/790i chipsets (tested) 2022-07-17 20:28:58 +02:00
martinwhitaker
e6e0f0c8e7
USB improvements (#116)
* Add new heap manager.

* Convert OHCI driver to use new heap manager.

* Convert UHCI driver to use new heap manager.

* Convert EHCI driver to use new heap manager.

* Convert XHCI driver to use new heap manager.

* Convert SMP to use new heap manager.

* Add a "usbinit" boot option to handle various buggy USB devices.

This replaces the "keyboard=buggy-usb" option, and adds a second
workaround to handle the problem seen in issue #107.
2022-07-16 13:34:08 +02:00
Sam Demeulemeester
89e2643de4
Add AP Enumeration to distinguish P-Core from E-Core on Hybrid CPUs (#62)
Add AP Enumeration to distinguish E-Core from P-Core on Intel Hybrid CPUs, and exclude them from the selected cores by default.  Including E-Cores slows down some tests and takes longer to catch memory errors.

A new exclude_ecores flag has been added in config.c to include E-Cores if needed.
2022-07-16 13:28:53 +02:00
Sam Demeulemeester
6b998e82e7 [TTY/Serial] Always use absolute positioning instead of relying on CR-LF 2022-06-19 16:47:10 +02:00
01e3
1c88824a7d
Optimize screen & serial output handling. (#85)
- Enable VGA/FB to output box drawing characters while maintaining VT100
   character set for serial. Shorten and simplify the screen setup code.

 - Track the background color to decide if the serial output needs to be
   inverted. Remove no longer needed logic for known areas of the screen that
   need to be inverted. As a bonus - popup menu can now be also inverted on
   serial.

 - Reduce the amount of data sent to serial by using CR+LF when possible
   instead of always relying on absolute positioning. Add tty_print()
   for positioning the cursor, remove no longer needed tty_print().

 - Remove no longer needed "LF -> LF+CR" logic from serial_echo_print().

Before (gcc-11.3.0-x86_64):
      text       data        bss      total filename
       929        357         64       1350 system/serial.o
      3517       1356         54       4927 app/display.o

After (gcc-11.3.0-x86_64):
      text       data        bss      total filename
       907        336         64       1307 system/serial.o
      3442       1242         54       4738 app/display.o

Co-authored-by: Sam Demeulemeester <38105886+x86fr@users.noreply.github.com>
2022-06-19 16:40:30 +02:00
Sam Demeulemeester
680e6ad79b Typo on smp.c (missing ;) 2022-06-19 16:39:03 +02:00
Sam Demeulemeester
231b389b3c Various minor cosmetic changes on acpi.c/h (mainly comments and code format) 2022-06-19 16:39:03 +02:00
Sam Demeulemeester
a5576974cf Add ACPI Timer as the primary TSC correction source and PIT Timer as fallback 2022-06-19 16:39:03 +02:00
Sam Demeulemeester
eac4d03462 Parse FADT to find ACPI Timer Base Address and specs 2022-06-19 16:39:03 +02:00
Sam Demeulemeester
cee2d32766 Add a few ACPI Tables Signature that could be useful later 2022-06-19 16:39:03 +02:00
Sam Demeulemeester
221a66da1a Split ACPI Functions from SMP functions.
Add ACPI Table detection for FADT & HPET (as we need better timers)
2022-06-19 16:39:03 +02:00
Lionel Debroux
63a07258fd Fix the operation of the SMBus functions which require the SMBus controller ID. 2022-06-08 18:00:50 +02:00
Sam Demeulemeester
7758adfb9d Improve readability on disabled code 2022-06-06 22:24:09 +02:00
Sam Demeulemeester
106eabef98 Fuse HYGON and AMD because the SMB controllor is strictly identical on both 2022-06-06 22:24:09 +02:00
Lionel Debroux
e86b04a14a Perform major simplification in smbus.c to reduce code size while keeping the functions readable, removing several unused strings and unnecessary arguments passed to several functions.
Add a bunch of PCI device IDs and driver indications for other SMBus controllers, so as to avoid other persons having to do that work again.
Add support for two PIIX4 devices: the standard PIIX4 PCI device ID, and the ServerWorks CSB5, which has a slight twist.

Co-authored-by: Lionel Debroux <lionel_debroux@yahoo.fr>
Co-authored-by: Sam Demeulemeester <sam@x86.fr>
2022-06-06 22:24:09 +02:00
Sam Demeulemeester
6cd356f831 Add External L2 detection for ALi Aladdin V Chipset (#87) 2022-06-06 19:56:04 +02:00