Commit Graph
501 Commits
Author SHA1 Message Date
Sam Demeulemeester 7eb2568dfe Add support for Intel Lunar Lake & Panther Lake CPUs 2026-03-23 17:52:55 +01:00
Sam Demeulemeester a90edd63ce Fix tRP measurement on Intel LPDDR5 laptop
Use tRPpb instead of tRPab
2026-03-23 17:52:02 +01:00
Sam Demeulemeester 82bb87a710 Early bump to v8.10 2026-03-17 00:37:45 +01:00
Sam Demeulemeester e486dde638 Fix shadowed var declaration and whitespaces issues in config.c 2026-03-17 00:37:18 +01:00
Sam Demeulemeester feeb7d2d01 Fix Core Topology Determination on some CPUs (eg: Intel PTL) 2026-03-17 00:15:46 +01:00
Sam Demeulemeester 4fa58699a9 Add support for x2APIC (#583)
* First commit to support x2APIC

* Keep apio_x2apic bool everywhere to avoid compilation issues on LA64.
x2APIC support on LA64 must be checked later (probably different MSRs)

* Various fixes
 - Fix flags in MADT x2APIC (CPU only has ENABLED, not ONLINE
 - Increased chunk index and related function from 8 to 16-bit
 - Increase MAX_APS and MAX_APIC_IDS to 512 (need an APs stack size evaluation to be sure we will not overflow)
2026-02-14 13:35:45 +01:00
Dongyan Qian 450961c81e system/loongarch: Fixes display issues for 2K3000/3B6000M (#589)
On LoongArch, PCIe MMIO space above 4 GiB must be mapped as uncached;
otherwise writes may not reach the device, so framebuffer updates are not visible.
Adjust the PCIe memory window layout according to the Loongson 2K series documentation.

Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
2026-01-29 11:05:07 +01:00
Jonathan Teh d39efcdcda hwquirks: Detect cache on VIA VP/VPX (#576)
Extend the existing quirk for VP3/MVP3 to VP/VPX.
2026-01-19 01:09:58 +01:00
Yao Zi 1c075f8cd0 system: loongarch: cpuinfo: Unroll memspeed copy loop (#578)
Unlike x86_64 where rep movsl/movsq could be turned into efficient uOP
to achieve a good performance, on LoongArch a simple loop that copies
only 8 bytes per iteration couldn't fully feed the pipeline.

This makes calculated cache bandwidth suspcious: on my Loongson 3A5000
laptop, memtest86plus reports the same bandwidth for L1 and L2, which is
obviously incorrect.

Let's unroll memspeed loop to copy 64-bytes per iteration, which fits
in a cacheline and should fully feed the pipeline for even future
generations of Loongson cores.

Signed-off-by: Yao Zi <me@ziyao.cc>
2026-01-19 01:09:19 +01:00
martinwhitaker 213285adab Work-arounds for issues with Fedora GRUB EFI "linux" command (#572)
* Extend the header size to 4KB align the code segment in the image file.

A recent change (commit e41655885) to the Fedora implementation of the
GRUB "linux" command for EFI boot means it now loads the entire image
(including the header) at the preferred load address instead of just
loading the code section. This means the code section is no longer 4KB
aligned. In our image, the code section contains the combined .text and
.data sections, so this means the .data section is also no longer 4kB
aligned, which results in a GPF when the startup code loads the new page
directory address into CR3.

Work around this issue by extending the header size to force the code to
start on a 4KB boundary.

* Disable memory write protection after EFI setup.

A recent change (commit e41655885) to the Fedora implementation of the
GRUB "linux" command for EFI boot means it now attempts to make the
loaded code section read-only, using the EFI_MEMORY_ATTRIBUTE_PROTOCOL.
In our image the code section contains the combined .text and .data
sections. Our startup code needs to write to the .data section before
we can switch to our own page descriptor table, so globally disable
write protection as soon as we return from efisetup().

Our page descriptor table makes all pages writable (we need to be able
to write to memory to test it), so there's no need to reenable the
write protection once we've made the switch.

I have no UEFI firmware that implements the EFI_MEMORY_ATTRIBUTE_PROTOCOL,
so this fix is not yet proven.
2026-01-19 00:51:27 +01:00
Gabriel Mongaras 1f0baf7a95 Added testlist to boot options (#570) 2025-11-29 13:24:46 +01:00
Tormod Volden bd03d8a6a1 debug_memtest.sh: Extract offsets (also BSS) from code and binary (#562)
* debug_memtest.sh: Extract offsets from code and binary

Split the Init function so that the binary is built before creating the
gdb script.

The offsets most often subject to change are now determined
automatically instead of being hard-coded.

Signed-off-by: Tormod Volden <debian.tormod@gmail.com>

* debug_memtest.sh: Extract and pass BSS offset to gdb

Signed-off-by: Tormod Volden <debian.tormod@gmail.com>

---------

Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
2025-11-24 00:58:58 +01:00
Tormod Volden 492ca4f67f Avoid glitch in runtime hours display when time is reset (#561)
Use a space-padded width of two for displaying the hours.

Otherwise, if the hours had been 2 digit, the last digit from the
seconds would linger after the hours were going 1 digit again.

Fixes #560

Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
2025-11-24 00:58:23 +01:00
dependabot[bot]anddependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> 79a670dfbd Bump actions/checkout from 5 to 6 (#564)
Bumps [actions/checkout](https://github.com/actions/checkout) from 5 to 6.
- [Release notes](https://github.com/actions/checkout/releases)
- [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md)
- [Commits](https://github.com/actions/checkout/compare/v5...v6)

---
updated-dependencies:
- dependency-name: actions/checkout
  dependency-version: '6'
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
2025-11-24 00:53:31 +01:00
Lionel Debroux 778cf00e1d Minimal fixup for #405: the 32-bit x86 binary started freezing reliably and quickly after 6f4ec848c4e9291626236bca457baf7b95542325; in app/main.c::run_at(), change the way the jump to the new start_address is performed on 32-bit x86. v8.00 2025-10-26 09:50:17 +01:00
martinwhitakerandSam Demeulemeester 3a7a058aed Recognise VT52/VT100/VT220 key escape sequences on serial console (#547)
* Recognise VT52/VT100/VT220 key escape sequences on serial console.

Map function keys to '0' to '9' and cursor keys to 'u', 'd', 'l',
'r', as is done for legacy and USB keyboards. Ignore all other
special key sequences.

* Make serial_echo_print() and tty_goto() static.

These are local to serial.c. Making them static saves a few bytes.

* Update keyboard.h to document cursor key mapping.

* Added some escape codes for terminals & VT100+
Change input order to check TTY first

* Replace comments about PF6-10

---------

Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
2025-10-08 12:51:49 +02:00
Lionel DebrouxandCalvin Owens 6f4ec848c4 Help the code build with contemporary Clang & LLD. (#405)
* rework the PTE definition macros to completely avoid recursivity, so as not to have to special-case Clang which has a low default recursivity limit;
* replace a non-portable goto construct in app/main.c;
* make tools overridable in i586 and x86_64 Makefiles;
* let go of --warn-constructors flag to ld: lld doesn't support it and ld's manual indicates that it does nothing on COFF and ELF;
* don't discard .shstrtab section: lld somehow requires it, and keeping it doesn't change the final binary on ld anyway;
* don't discard .rela.dyn: lld produces an improper binary otherwise, but it doesn't change the final binary with ld;
* use out of line versions of memcpy() and memset() on Clang: sadly, the built-in versions are not up to the task of generating efficient inline versions.

Co-authored-by: Calvin Owens <calvin@wbinvd.org>
2025-10-07 15:39:22 +02:00
Sam Demeulemeester 6af76b804b Enable DDR5 Temperature polling 2025-10-07 15:38:27 +02:00
Sam Demeulemeester ced9529bea DDR5 DIMM Temperature Reporting (#497)
* Initial commit for DDR5 Temperature report

* Change smbus.h to i2c_x86.h

* Change I2C includes defines name to avoid conflict

* Add dummy get_ram_temp() function on LA64

* Add menu option for RAM/DDR5 Temperature polling
2025-10-06 23:01:33 +02:00
David Corvaglia 2b51351ab7 added serial newline option (#528) 2025-10-05 16:53:19 +02:00
Sam Demeulemeester ae9e085035 Add support for AMD Zen5 Granite Ridge (GRG) ECC polling. (#545)
Fix an issue with Rembrandt ECC polling where only half of the channels where checked
2025-10-05 16:35:53 +02:00
Sam Demeulemeester 2350230351 Unhide SMBUS device to allow SPD reading on early Intel's ICH SB (#544)
* Add quirks for ICH0-5 (SMbus Unhide)

* Minor constant name changes & typo
2025-10-05 16:31:55 +02:00
Sam Demeulemeester ac7d092417 Added various DRAM manufacturers from JEP106 list
Manually reworked strings
2025-10-05 16:26:58 +02:00
Sam Demeulemeester 6888b1d5a0 Add support for Intel Arrow Lake-H (SOC)
Tested OK on NUC 15th Gen.
2025-10-05 16:02:07 +02:00
Lionel Debrouxand01e3 a935afd50a Avoid unnecessary Frame Buffer updates (#543)
Frame Buffer updates are expensive, let's instead uses these CPU cycles
for testing RAM...

Co-authored-by: 01e3 <01e3@ans.pl>
2025-09-14 21:36:34 +02:00
dependabot[bot]anddependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> 18a25d4dc4 Bump actions/stale from 9 to 10 (#541)
Bumps [actions/stale](https://github.com/actions/stale) from 9 to 10.
- [Release notes](https://github.com/actions/stale/releases)
- [Changelog](https://github.com/actions/stale/blob/main/CHANGELOG.md)
- [Commits](https://github.com/actions/stale/compare/v9...v10)

---
updated-dependencies:
- dependency-name: actions/stale
  dependency-version: '10'
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
2025-09-14 21:35:08 +02:00
martinwhitaker 2a58a7cb53 Add USB hub quirk to support AMI virtual keyboard (issue #523) (#535)
* Add USB hub quirk to support AMI virtual keyboard (issue #523)

From testing it appears that the AMI virtual devices do not work
correctly if you disable one port on the virtual hub then reuse the
USB address for a device connected to another port on that hub. So
add a quirk to detect the virtual hub from its vendor/product ID
and leave all ports on that hub active when performing the scan for
USB keyboards. This will permanently reserve a bit more memory, but
not significantly so.

* Replace hard-coded USB vendor ID with macro definition.
2025-08-16 22:20:40 +02:00
Lionel DebrouxandSam Demeulemeester f19066d258 Update Intel i801 PCI device IDs list & Add support for MTL-P (#537)
* Update Intel i801 PCI device IDs list from the Linux driver.

* Add support for MTL-P (eg: NUC 14th Gen)

---------

Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
2025-08-14 12:17:27 +02:00
dependabot[bot]anddependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> ed4947e83c Bump actions/checkout from 4 to 5 (#536)
Bumps [actions/checkout](https://github.com/actions/checkout) from 4 to 5.
- [Release notes](https://github.com/actions/checkout/releases)
- [Changelog](https://github.com/actions/checkout/blob/main/CHANGELOG.md)
- [Commits](https://github.com/actions/checkout/compare/v4...v5)

---
updated-dependencies:
- dependency-name: actions/checkout
  dependency-version: '5'
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
2025-08-14 11:41:04 +02:00
Jonathan Teh 1b5065b494 imc: Enable support for AMD Cezanne (Zen 3 APU) (#525) 2025-07-06 13:06:38 +02:00
Martin Whitaker 106f9ee358 Add optional parameters to usbdebug boot option.
The usbdebug option may now be optionally followed by "=hub" or "=kbd",
which enables details of the configuration and endpoint descriptors to
be printed when scanning for hubs or keyboards respectively. This can
easily result in more than one screenful of information (and we can't
say "press any key to continue" before we've completed the scan and set
up the keyboard handler), so a 1 second delay is added after printing
each line of detailed information.
2025-07-04 18:04:09 +01:00
Sam Demeulemeester 2f9b165eec Add support for AMD Hawk Point FP7 (Phoenix) 2025-05-27 22:02:41 +02:00
Dongyan Qian 07d84f4f34 loongarch: Supports 2K2000/3B6000M (#512)
* loongarch: adjust 2K/3B6000M DDR rate factor
* loongarch: Supports fewer cache layers than L3

For example: 2K2000 chip does not have L3, but has L2.
If L2Cache is not flushed to memory, it will cause read and write data errors after cache_off.
2025-05-12 13:56:30 +02:00
Sam Demeulemeester 4d08b14a3d Remove Ubuntu 20.04 from workflows due to deprecation 2025-04-20 19:22:33 +02:00
Sam Demeulemeester a47b2bc053 Fix DDR5 SPD parsing issue for XMP 3.0 frequency
On DDR5, limit XMP profile parsing to 2 to avoid conflict between XMP and EXPO
Add a check to skip very low tCK values
2025-04-20 19:16:51 +02:00
Chao Li 3cb2cdd62a Updated README and adjusted Makefile for LoongArch64 (#499)
* build: Change the memtest.efi to mt86plus on LoongArch

Change the main binary from memtest.efi to mt86plus.

* build: Add GRUB iso support on LoongArch64

Enable the GRUB iso support on LoongArch64, it requires the LoongArch64
Linux ENV, so it is not possible create it on x86-64 Linux ENV.

* README: Add LoongArch content

Added LoongArch info and how to build, adjusted some style.

Signed-off-by: Chao Li <lichao@lonogson.cn>
2025-04-06 14:16:53 +02:00
Lionel Debroux a10664a251 Make paths more uniform across architectures; adjust the build system and Github workflows accordingly.
* move x86/x86-64-specific files to boot/x86, build/i586, build/x86_64, system/x86, system/imc/x86;
* move build64/la64 to build/loongarch64;
* rename system/imc/loongson to system/img/loongarch.
2025-02-24 20:25:29 +01:00
Sam Demeulemeester 3b1d85291d Change README.md to add recently added 'dark' mode 2025-02-10 23:39:13 +01:00
Sam Demeulemeester 97de11f9f5 Add support for color schemes and implement a dark mode (#496)
Color vs Colour. That is the question.
Closes #439
2025-02-10 23:33:48 +01:00
Sam Demeulemeester 9053696e12 Switch Address Tests from SEQ to ONE for Faster Error Detection on HCC CPUs (#485)
* Change Address tests from SEQ to ONE for (much) faster startup on HCC CPUs
This change will dramatically decreases the time needed to find the first fault on high core count CPUs by switching the address tests from all cores to one core.
There is probably no (or very very few) cases where a computer will be allowed to pass basic POST if all cores can't reach all areas of the RAM, so this is probably the way to go

* Removed and excluded mt8plus binary and switched Test #1 to ONE
2025-02-06 14:14:38 +01:00
Lionel Debroux e5c4800e58 Github workflow: test build on Ubuntu 24.04 as well. (#488) 2025-02-06 14:09:52 +01:00
Chao Li 37f8bae2dc build64: Fix iso creation on LoongArch (#490)
Ubuntu 24.04 uses xorriisofs V1.5.6, which checks for hybird formats
when `-part_like_isohybird` is used, and will report the core dump if
the MBR is not included.

Removed the `-part_like_isohybird` option on LoongArch to fix it, and
only use EFI boot mode on LoongArch.

Signed-off-by: Chao Li <lichao@loongson.cn>
2025-02-06 13:46:44 +01:00
martinwhitaker e285fbb4b9 Ignore PS/2 mouse events (issue #456) (#484)
If a legacy BIOS has enabled PS/2 mouse input, the bytes received on
port 0x60 may come from either the keyboard or the mouse. Currently
we treat all bytes as keyboard input, which means mouse input will be
translated into arbitrary key codes. This may cause a memory test to
be interrupted or aborted. We should instead disable or ignore any
mouse input.

Although it should be possible to reconfigure the PS/2 controller to
disable mouse input, it's quite likely that there's some quirky H/W
out there that makes this more complicated than it seems. The simple
solution is to detect mouse input by checking whether bit 5 of the
received byte is set and discarding it if so.
2025-01-27 21:54:54 +01:00
01e3 71d061a4c7 Merge bootsect.S and setup.S into header.S (#467)
* Merge bootsect.S and setup.S into header.S

Currently, Memtest86+ provides two (three counting mbr.S) different
headers: bootsect.S and header.S that together with setup.S are used
to build the final binaries:
 - bootsect.S for booting from the legacy BIOS, used in memtest.bin.
 - header.S for booting from the UEFI, used in memtest.efi.

Both support loading by an intermediate bootloader. Also, both are
derived from the Linux kernel, but from a very different chapter in its
evolution. FDD loading was removed a very long time ago, many, many
years before adding PE/COFF headers for UEFI. Also, the PE/COFF headers
are large (even larger for x86-64) and take a lot of very limited space,
leaving almost no headroom for the actual code.

This commit merges bootsect.S and setup.S into header.S adding BIOS
(FDD) loading support, which should eventually enable to maintain a single,
all-in-one binary that can be booted either by an intermediate bootloader
(such as GRUB or LILO), UEFI and BIOS. Easier and less confusing for users,
as I have continued to see cases when people assume memtest.bin is needed
for non-UEFI systems, even if never intended for FDD loading.

To ensure we have enough space for both the boot code (limited to 512B
including Linux boot header and address of the New EXE header) and
UEFI headers, the PE/COFF headers got moved into the ".setup" section
of the code where *currently* we have 1024B total and about 90B free.
Should more space be needed in the future, we can grow that section or
perhaps even better - move PE/COFF into its own section that will not
even need to be loaded.

Overall, the code got copied from bootsect.S and setup.S with very, very
minimal changes, most importantly:

 - Dedicated routine for printing strings (print_string) got added and
   lives in the ".bootsect" section.

 - Print "Loading " message almost immediately after BIOS loads and
   calls code from the .bootsect" section, even before setting up
   the custom FDD parameter table. The sooner the better.

 - Set DX to 0x0000, as the code depends on its value. While the BIOS is
   expected to set DL register to the boot drive number which is 0 for FDD,
   to my knowledge there is no guarantee for DH to have any particular
   value. Also, when executing "MZ" signature as x86 instructions,
   the original value of DX becomes instantly and irrevocably lost. This
   is fine as we only support booting from FDD anyway.

 - Print "Memtest86+" and its version after loading the ".setup" section.
   We can get the string from mt86plus_version (kernel_version), no need
   to duplicate in the boot sector where we are very space limited and as
   a bonus we can provide the version information.

As diffstat shows a lot of code changed and added, it may be easier use
the following commands:
 diff -Nur bootsect.S header.S
 diff -Nur setup.S header.S

While there are several more changes and fixes I would like to make in the
boot code (some of them were already included in the earlier RFC version
[1] before we got UEFI signing support added) for now I tried this to be as
least disruptive as possible and avoid unnecessary code changes to make
the review easier.

[1] https://github.com/memtest86plus/memtest86plus/pull/136

* Bye bye memtest.bin and memtest.efi, long live mt86plus

With the efi binary providing the BIOS floppy loading functionality,
there is no need to support separate memtest.bin file any longer.

Remove memtest.bin from {build32,build64}/Makefile, replace memtest.bin
amd memtest.efi with mt86plus eveywhere to avoid confusion with
other memtests.

Also, unify build32/Makefile and build64/Makefile by removing
unnecessary differences between them, like extra spaces or
different OBJS order.

Finally, update README.md, HOW_TO_DEBUG_WITH_GDB.md and other
places that had a reference to memtest.{bin,efi}. Note that for
debug_memtest.sh, mt86plus.efi is used.
2025-01-27 19:43:24 +01:00
Sam Demeulemeester b51c6e75f3 Add Thermaltake and SSTC Jedec IDs 2025-01-27 19:41:36 +01:00
Sam Demeulemeester a65857b702 Early bump to v8.00 2025-01-27 19:28:03 +01:00
Chao Li 422212b06a system/hwquirks: Optimization Loongson 7A2000 EHCI quirk (#473)
Currentilly, it only compares the root bus DID is 0x7A00 which sometimes
fails, a new logic was added to compare the 7A2000 EHCI DID to fix it.

Signed-off-by: Chao Li <lichao@loongson.cn>
2024-12-06 22:51:18 +01:00
Sam Demeulemeester bdefff91ce Fix LD error while linking LoongArch EFI binary (#457) 2024-11-25 17:39:00 +01:00
Sam Demeulemeester 5a046291fa Add a few RAM manufacturers in JEDEC DB 2024-11-12 00:25:38 +01:00
Jonathan TehandSam Demeulemeester 51b78487f5 hwquirks: Detect cache on VIA VP3/MVP3 (#356)
Add quirk to detect motherboard cache on VIA VP3/MVP3.

Co-authored-by: Sam Demeulemeester <38105886+x86fr@users.noreply.github.com>
2024-11-12 00:10:40 +01:00