* cpuinfo: Fix WinChip and Cyrix/NSC CPU name and cache info
Always populate the cache info from extended CPUID, it is not used for
Intel CPUs, even though it is present, and is useful for non-Intel CPUs.
Fix the CPU name and cache sizes for Centaur and Cyrix/NSC CPUs without
brand string, which are the WinChip C6 and all Cyrix CPUs except the
Media GXm.
For the Media GXm and Geode GXm/GXLV/GX1, which are available with both
Cyrix and NSC vendor strings, hardcode the L1 cache size. The Geode GX2
uses standard cache info.
* Add 'Intel' in CPU names for older CPUs
* Add 'Transmeta' and 'IDT' in CPU names for older CPUs
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Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs
Use extended CPUID for VIA C3/C7/Nano cache information.
Use MSR reads for Nano/Zhaoxin and VIA C7 processor temperature.
Tested on VIA C7-D 1.5GHz.
* Small code conventions fixes
* Fix overallocation of cpuid_cache_info_t union (From PR #263)
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Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
Some CPU like Intel Yorkfield (Core 2 Quad) reports max CPUID > 0xB but doesn't support CPUID = 0xB. Check x2apic flag to be sure CPUID 0xB is supported. If not, fallback to older detection method
Add AP Enumeration to distinguish E-Core from P-Core on Intel Hybrid CPUs, and exclude them from the selected cores by default. Including E-Cores slows down some tests and takes longer to catch memory errors.
A new exclude_ecores flag has been added in config.c to include E-Cores if needed.
