Calling clear_screen_region to erase the screen section and then
immediately calling printf/prints to write the new information is
sub-optimal as the screen gets updated twice.
This is especially expensive when Frame Buffer is used.
This also creates an unpleasant flickering effect with quickly changing
information, like test patterns.
Introduce printf_region and prints_region macros to call printf / prints
and then clear_screen_region to clear only the region outside the printed
area.
For consistency, also convert all display_cpu_topo_* macros.
Next, avoid redundant screen clearing in display_start_test:
- display_test_number already takes care of padding,
- test description gets updated immediately after, no need to clear
that region.
Finally, simplify the code by adding SCREEN_MAX_COL to define the maximum
column of the screen, so it can be used instead of SCREEN_WIDTH - 1.
WRMSR to the x2APIC MSRs is not serializing, so an IPI could be sent
before older stores (eg: the barrier wakeup flags) are globally visible,
deadlocking the woken CPU on stale data.
Insert MFENCE;LFENCE before the ICR write, as required by the
Intel SDM (vol 3A, 11.12.3) and matching the linux kernerl
weak_wrmsr_fence(). The need for lfence is mostly black magic...
Find the boot CPU's APIC ID in the table and move it to slot 0, otherwise
smp_start() sends INIT-SIPI to the BSP itself and hangs the system.
Also skip entries whose APIC ID is already listed, as some firmwares
declare the same core as both a local APIC and an x2APIC entry.
This is a strict violation of the ACPI specs, but it happens...
* Initial commit for ARM64 (header.S & startup.S)
* Add Aarch64 interrupt handler
* Adapt lib/ to Aarch64
* Small ASM addition for AArch64
* Rewrite Aarch64 system/
- cpuid.c/cpuinfo.c for CPU detection (Qualcomm, Apple, Nvidia, etc)
- Add ARM Power State Coordination Interface (PSCI) functions
- vmem.c for Virtual Memory MAnagement on ARM64
- Various functions placeholders
* Add pseudo-TSC correction for Aarch64
* Add pseudo-tsc measurement for Aarch64
* Add Aarch64 if/elif on basic IO/MMIO/MEM RW functions
* Add support for Surface 13 / Snapdragon X KB USB
Fix an issue with the XHCI.c drivers with packets > 8 bytes
* Add MMIO Serial support for ARM64
* Add ARM64 ASM for block_move & mov_inv_fixed. Fix VM start pointer
* Add ARM Serial MMIO configuration
* Revert previous commit & reintroduce ARM64 cache functions
* Add ACPI MCFG Table description & SMP parsing. This requires careful review/testing to avoid BC issues!
* Revert previous commmit and reintroduce relocation and heap change for ARM64
* ARM64 does not support CPU PNS. Use DMI type4 parsing instead. Add SMBIOS v3 support (ARM64 does not support v2)
* Fix typo in pci.h
* Move Aarch64 load-limit computation from main.c to pmem.c
* Add .arm64 to version string. Use PMU for clock computation display. Fix D5 Temp NULL not handled
* Add Makefile and linker scripts for aarch64. Set cross-compiler from x86 by default
* Attempt to add aarch64 to workflow
* Remove a remaining internal debug flag
* Correct typos
* Fix ARM64 SMP freeze
assign heap when RAM is one contiguous region, keep it below 3GB for DMA (RPi5), add DSB before SEV to avoid missed barrier wakeups
Sync I-cache with D-cache after program relocation to prevent stale instruction fetch
* Validate MADT entry lengths to avoid reading past the table (or looping forever) on malformed ACPI tables
* aarch64: add NEON kernels for the vector PRSG tests
Tests 3 (bus stress) and 5 (moving inversions, random) now dispatch to 128-bit NEON fill/scan instead of scalar.
* Fix ARM64 data abort from the per-second DMI check & fix unbounded strstr()
* Fix ARM64 data abort when saving results to USB after a relocation
* Update README.md with AArch64 (ARM64) support
* aarch64: shrink static string tables, harden MCFG/paging
Replace pointer-based name tables with inline char arrays (saves ~1.5KB + relocs)
alidate MCFG length/bus ranges, and bound pm_map/vm_map fills against overflows
* Add NVIDIA & latest Apple ARM SoC to cpuid.c
* Fix stale pointers read by the report writer after a program relocation
cpu_model gets a static init (creates its reloc record)SPD type becomes an inline char array
* Initial commit for USB Mass Storage Support
* Add support for SCSI_16 and various fixes by debrouxl
* Fix USB HCD registration to skip failed probes (when a mass storage device was already found)
* Fix xHCI bulk transfer completion matching & accept short packets for IN transfers
* Add USB BOT error recovery and match xHCI control events by slot/EP
* Add EHCI bulk timeout/size guard, fix per-controller MSD port handling, and make xHCI keyboard re-arm precise
* Harden FAT/GPT parsing (cluster validation & block-size check) and fix RTC read issue due to R/W race
* Fix report varargs on x86_64, truncate F6 drive label, and clean up failed FAT file writes
* Fix stale hub VID/PID read, refactor USB MSD detection to helper & tidy usbhcd/display/config layout
* Scan for USB drives on demand when saving a report
Keep EHCI/xHCI controllers registered when empty and rescan free root ports on F6.
Also fix xHCI keyboard re-arm losing a key release, dropping the next same-key press.
* Display memory info from DMI when SPD is unavailable
* ARM64 does not support CPU PNS. Use DMI type4 parsing instead. Add SMBIOS v3 support (ARM64 does not support v2)
* Hardened AP Stack Management (see PR for details)
* Fix low-memory boot issues caused by the larger AP stack area
Zero only _bss.._stacks at first boot (the full sweep wiped ACPI/SMBIOS anchors above 0xE0000 on writable-shadow platforms), verify relocation addresses against pm_map, and relocate before smp_start() when the enabled CPUs' stacks would extend beyond usable low RAM, setting up the AP trampoline at start time.
Blacksmith-style non-uniform, REFRESH-synchronised many-sided hammering with DRAMA-lite row-stride discovery and a blind-stride fallback
x86 clflush(opt) engine with a coarse whole-cache-flush fallback for other targets. LA64 TBT
Two per-CPU streams alternate NT-store bursts of a fresh PRSG sequence with read-verify of the previous round, forcing write-to-read turnarounds and row conflicts; odd rounds insert idle gaps to provoke PMIC load steps. Targets DDR5-era interface faults (link SI, marginal XMP/EXPO training, voltage droop) that on-die ECC cannot correct
Moving PRSG vector kernels from mov_inv_rng.C to a shared module in tests/
Run the random sequence test (now #4) and Modulo-20 (now #6) before the 64-bit shifting pattern test (now #8), so that every fault class is probed early in the pass.
Trade the walker's redundant repetitions (3 -> 1 iteration, plus only every other offset on the fast first pass) for more never-repeating work (random sequence 24 -> 96 rounds, Modulo-20 6 -> 9), at unchanged pass time.
Replace tests 5 & 8 with a single moving inversions test using per-lane
xorshift sequences and non-temporal stores. Kernels (inline asm) are picked
at runtime via the new system/simd module: AVX2, SSE2 or scalar, with the
tier shown in the test name.
Fix and enable the AVX/XCR0 startup code and decode the XSAVE/AVX/AVX2 CPUID flags.Suite shrinks from 11 to 10 tests.
Adds external L2 cache size detection for Socket 7 boards with SiS 530
northbridge, and extends the existing ALi quirk to also cover Aladdin IV
(M1531) in addition to Aladdin V (M1541).
Tested on: K6-II + SiS 530 with 512KB L2 cache.
Closes#602
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Enable SSE2 on x86_64 build
* Better Memory Bandwidth measurement
- Moved memory speed measurement to a dedicated file
- Use SSE2 on x86_64 for better DRAM BW measurements
- Add a lot of safeguards to avoid issue with very large L3 cache
- Add a more precise way to target a specific cache
- Change the iteration number from fixed to time-constrained so overall test time is always same
- Added many configuration parameters for fine-tuning
* Revert saving XMM registers to stack.
Instead, make sure to use only GPR for interrupt handling (so it won't touch SIMD regs)
* system/loongarch: Decode CPU temperature as signed 8-bit
Interpret the low 8 bits of the CPU temperature register as a signed
value, apply the platform-specific offset, and reject readings when the
temperature-valid bit is clear.
At low temperatures the raw register value would otherwise be interpreted
as a large positive number, which breaks the displayed reading.
Reported-by: Mingcong Bai <jeffbai@aosc.io>
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* Better display of CPU temp from -99°C to 999°C
* Add sentinel value for CPU_TEMP_INVALID to allow negative temperature
---------
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
Some modern UEFI refuse to load PE image when a section have both IMAGE_SCN_MEM_WRITE and IMAGE_SCN_MEM_EXECUTE flag set. The .text section was using both because relocation need to write in data area.
Split the .text PE section in two: .text with read-execute only for code and rodata, and .data with read-write for dynamic, data and got. Also set IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag accordingly (we only need it for startup and not when Memtest86+ is running later).
For x86 and LoongArch headers:
- NumberOfSections go from 3 to 4
- Remove IMAGE_SCN_MEM_WRITE from .text section
- Add new .data section with RW flag, no execute
- Fix SizeOfInitializedData to include .data and .sbat
- Set IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag
- BaseOfData now point to .data instead of .sbat (PE32)
- .dynamic moved after relocation tables (memtest_shared.lds)
- page-aligned _etext_ro symbol used as read-only/writable boundary (memtest_shared.lds)
* Correct the format of sbat.csv
* Use real size for sbat section to avoid issue with shim parsing
* Trying to find why shim doesn't load it...
No success yet...
* First commit to support x2APIC
* Keep apio_x2apic bool everywhere to avoid compilation issues on LA64.
x2APIC support on LA64 must be checked later (probably different MSRs)
* Various fixes
- Fix flags in MADT x2APIC (CPU only has ENABLED, not ONLINE
- Increased chunk index and related function from 8 to 16-bit
- Increase MAX_APS and MAX_APIC_IDS to 512 (need an APs stack size evaluation to be sure we will not overflow)
On LoongArch, PCIe MMIO space above 4 GiB must be mapped as uncached;
otherwise writes may not reach the device, so framebuffer updates are not visible.
Adjust the PCIe memory window layout according to the Loongson 2K series documentation.
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Unlike x86_64 where rep movsl/movsq could be turned into efficient uOP
to achieve a good performance, on LoongArch a simple loop that copies
only 8 bytes per iteration couldn't fully feed the pipeline.
This makes calculated cache bandwidth suspcious: on my Loongson 3A5000
laptop, memtest86plus reports the same bandwidth for L1 and L2, which is
obviously incorrect.
Let's unroll memspeed loop to copy 64-bytes per iteration, which fits
in a cacheline and should fully feed the pipeline for even future
generations of Loongson cores.
Signed-off-by: Yao Zi <me@ziyao.cc>
* Extend the header size to 4KB align the code segment in the image file.
A recent change (commit e41655885) to the Fedora implementation of the
GRUB "linux" command for EFI boot means it now loads the entire image
(including the header) at the preferred load address instead of just
loading the code section. This means the code section is no longer 4KB
aligned. In our image, the code section contains the combined .text and
.data sections, so this means the .data section is also no longer 4kB
aligned, which results in a GPF when the startup code loads the new page
directory address into CR3.
Work around this issue by extending the header size to force the code to
start on a 4KB boundary.
* Disable memory write protection after EFI setup.
A recent change (commit e41655885) to the Fedora implementation of the
GRUB "linux" command for EFI boot means it now attempts to make the
loaded code section read-only, using the EFI_MEMORY_ATTRIBUTE_PROTOCOL.
In our image the code section contains the combined .text and .data
sections. Our startup code needs to write to the .data section before
we can switch to our own page descriptor table, so globally disable
write protection as soon as we return from efisetup().
Our page descriptor table makes all pages writable (we need to be able
to write to memory to test it), so there's no need to reenable the
write protection once we've made the switch.
I have no UEFI firmware that implements the EFI_MEMORY_ATTRIBUTE_PROTOCOL,
so this fix is not yet proven.
01e3
Lionel Debroux
Sam Demeulemeester
Sam Demeulemeester
dependabot[bot]anddependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
Nikolaos Barkas
Michael Bemmerl
Dongyan QianandSam Demeulemeester
Jonathan Teh
Yao Zi
martinwhitaker