Adds external L2 cache size detection for Socket 7 boards with SiS 530
northbridge, and extends the existing ALi quirk to also cover Aladdin IV
(M1531) in addition to Aladdin V (M1541).
Tested on: K6-II + SiS 530 with 512KB L2 cache.
Closes#602
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Enable SSE2 on x86_64 build
* Better Memory Bandwidth measurement
- Moved memory speed measurement to a dedicated file
- Use SSE2 on x86_64 for better DRAM BW measurements
- Add a lot of safeguards to avoid issue with very large L3 cache
- Add a more precise way to target a specific cache
- Change the iteration number from fixed to time-constrained so overall test time is always same
- Added many configuration parameters for fine-tuning
* Revert saving XMM registers to stack.
Instead, make sure to use only GPR for interrupt handling (so it won't touch SIMD regs)
* system/loongarch: Decode CPU temperature as signed 8-bit
Interpret the low 8 bits of the CPU temperature register as a signed
value, apply the platform-specific offset, and reject readings when the
temperature-valid bit is clear.
At low temperatures the raw register value would otherwise be interpreted
as a large positive number, which breaks the displayed reading.
Reported-by: Mingcong Bai <jeffbai@aosc.io>
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* Better display of CPU temp from -99°C to 999°C
* Add sentinel value for CPU_TEMP_INVALID to allow negative temperature
---------
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
Some modern UEFI refuse to load PE image when a section have both IMAGE_SCN_MEM_WRITE and IMAGE_SCN_MEM_EXECUTE flag set. The .text section was using both because relocation need to write in data area.
Split the .text PE section in two: .text with read-execute only for code and rodata, and .data with read-write for dynamic, data and got. Also set IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag accordingly (we only need it for startup and not when Memtest86+ is running later).
For x86 and LoongArch headers:
- NumberOfSections go from 3 to 4
- Remove IMAGE_SCN_MEM_WRITE from .text section
- Add new .data section with RW flag, no execute
- Fix SizeOfInitializedData to include .data and .sbat
- Set IMAGE_DLLCHARACTERISTICS_NX_COMPAT flag
- BaseOfData now point to .data instead of .sbat (PE32)
- .dynamic moved after relocation tables (memtest_shared.lds)
- page-aligned _etext_ro symbol used as read-only/writable boundary (memtest_shared.lds)
* Correct the format of sbat.csv
* Use real size for sbat section to avoid issue with shim parsing
* Trying to find why shim doesn't load it...
No success yet...
* First commit to support x2APIC
* Keep apio_x2apic bool everywhere to avoid compilation issues on LA64.
x2APIC support on LA64 must be checked later (probably different MSRs)
* Various fixes
- Fix flags in MADT x2APIC (CPU only has ENABLED, not ONLINE
- Increased chunk index and related function from 8 to 16-bit
- Increase MAX_APS and MAX_APIC_IDS to 512 (need an APs stack size evaluation to be sure we will not overflow)
On LoongArch, PCIe MMIO space above 4 GiB must be mapped as uncached;
otherwise writes may not reach the device, so framebuffer updates are not visible.
Adjust the PCIe memory window layout according to the Loongson 2K series documentation.
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Unlike x86_64 where rep movsl/movsq could be turned into efficient uOP
to achieve a good performance, on LoongArch a simple loop that copies
only 8 bytes per iteration couldn't fully feed the pipeline.
This makes calculated cache bandwidth suspcious: on my Loongson 3A5000
laptop, memtest86plus reports the same bandwidth for L1 and L2, which is
obviously incorrect.
Let's unroll memspeed loop to copy 64-bytes per iteration, which fits
in a cacheline and should fully feed the pipeline for even future
generations of Loongson cores.
Signed-off-by: Yao Zi <me@ziyao.cc>
* Extend the header size to 4KB align the code segment in the image file.
A recent change (commit e41655885) to the Fedora implementation of the
GRUB "linux" command for EFI boot means it now loads the entire image
(including the header) at the preferred load address instead of just
loading the code section. This means the code section is no longer 4KB
aligned. In our image, the code section contains the combined .text and
.data sections, so this means the .data section is also no longer 4kB
aligned, which results in a GPF when the startup code loads the new page
directory address into CR3.
Work around this issue by extending the header size to force the code to
start on a 4KB boundary.
* Disable memory write protection after EFI setup.
A recent change (commit e41655885) to the Fedora implementation of the
GRUB "linux" command for EFI boot means it now attempts to make the
loaded code section read-only, using the EFI_MEMORY_ATTRIBUTE_PROTOCOL.
In our image the code section contains the combined .text and .data
sections. Our startup code needs to write to the .data section before
we can switch to our own page descriptor table, so globally disable
write protection as soon as we return from efisetup().
Our page descriptor table makes all pages writable (we need to be able
to write to memory to test it), so there's no need to reenable the
write protection once we've made the switch.
I have no UEFI firmware that implements the EFI_MEMORY_ATTRIBUTE_PROTOCOL,
so this fix is not yet proven.
* debug_memtest.sh: Extract offsets from code and binary
Split the Init function so that the binary is built before creating the
gdb script.
The offsets most often subject to change are now determined
automatically instead of being hard-coded.
Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
* debug_memtest.sh: Extract and pass BSS offset to gdb
Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
---------
Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
Use a space-padded width of two for displaying the hours.
Otherwise, if the hours had been 2 digit, the last digit from the
seconds would linger after the hours were going 1 digit again.
Fixes#560
Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
* Recognise VT52/VT100/VT220 key escape sequences on serial console.
Map function keys to '0' to '9' and cursor keys to 'u', 'd', 'l',
'r', as is done for legacy and USB keyboards. Ignore all other
special key sequences.
* Make serial_echo_print() and tty_goto() static.
These are local to serial.c. Making them static saves a few bytes.
* Update keyboard.h to document cursor key mapping.
* Added some escape codes for terminals & VT100+
Change input order to check TTY first
* Replace comments about PF6-10
---------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* rework the PTE definition macros to completely avoid recursivity, so as not to have to special-case Clang which has a low default recursivity limit;
* replace a non-portable goto construct in app/main.c;
* make tools overridable in i586 and x86_64 Makefiles;
* let go of --warn-constructors flag to ld: lld doesn't support it and ld's manual indicates that it does nothing on COFF and ELF;
* don't discard .shstrtab section: lld somehow requires it, and keeping it doesn't change the final binary on ld anyway;
* don't discard .rela.dyn: lld produces an improper binary otherwise, but it doesn't change the final binary with ld;
* use out of line versions of memcpy() and memset() on Clang: sadly, the built-in versions are not up to the task of generating efficient inline versions.
Co-authored-by: Calvin Owens <calvin@wbinvd.org>
* Initial commit for DDR5 Temperature report
* Change smbus.h to i2c_x86.h
* Change I2C includes defines name to avoid conflict
* Add dummy get_ram_temp() function on LA64
* Add menu option for RAM/DDR5 Temperature polling
* Add USB hub quirk to support AMI virtual keyboard (issue #523)
From testing it appears that the AMI virtual devices do not work
correctly if you disable one port on the virtual hub then reuse the
USB address for a device connected to another port on that hub. So
add a quirk to detect the virtual hub from its vendor/product ID
and leave all ports on that hub active when performing the scan for
USB keyboards. This will permanently reserve a bit more memory, but
not significantly so.
* Replace hard-coded USB vendor ID with macro definition.
* Update Intel i801 PCI device IDs list from the Linux driver.
* Add support for MTL-P (eg: NUC 14th Gen)
---------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
The usbdebug option may now be optionally followed by "=hub" or "=kbd",
which enables details of the configuration and endpoint descriptors to
be printed when scanning for hubs or keyboards respectively. This can
easily result in more than one screenful of information (and we can't
say "press any key to continue" before we've completed the scan and set
up the keyboard handler), so a 1 second delay is added after printing
each line of detailed information.
* loongarch: adjust 2K/3B6000M DDR rate factor
* loongarch: Supports fewer cache layers than L3
For example: 2K2000 chip does not have L3, but has L2.
If L2Cache is not flushed to memory, it will cause read and write data errors after cache_off.
* build: Change the memtest.efi to mt86plus on LoongArch
Change the main binary from memtest.efi to mt86plus.
* build: Add GRUB iso support on LoongArch64
Enable the GRUB iso support on LoongArch64, it requires the LoongArch64
Linux ENV, so it is not possible create it on x86-64 Linux ENV.
* README: Add LoongArch content
Added LoongArch info and how to build, adjusted some style.
Signed-off-by: Chao Li <lichao@lonogson.cn>
Sam Demeulemeester
Nikolaos Barkas
Sam DemeulemeesterandBerbe
Michael Bemmerl
Dongyan QianandSam Demeulemeester
Jonathan Teh
Yao Zi
martinwhitaker
Gabriel Mongaras
Tormod Volden
dependabot[bot]anddependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
Lionel Debroux
David Corvaglia
Chao Li