* Initial commit for ARM64 (header.S & startup.S)
* Add Aarch64 interrupt handler
* Adapt lib/ to Aarch64
* Small ASM addition for AArch64
* Rewrite Aarch64 system/
- cpuid.c/cpuinfo.c for CPU detection (Qualcomm, Apple, Nvidia, etc)
- Add ARM Power State Coordination Interface (PSCI) functions
- vmem.c for Virtual Memory MAnagement on ARM64
- Various functions placeholders
* Add pseudo-TSC correction for Aarch64
* Add pseudo-tsc measurement for Aarch64
* Add Aarch64 if/elif on basic IO/MMIO/MEM RW functions
* Add support for Surface 13 / Snapdragon X KB USB
Fix an issue with the XHCI.c drivers with packets > 8 bytes
* Add MMIO Serial support for ARM64
* Add ARM64 ASM for block_move & mov_inv_fixed. Fix VM start pointer
* Add ARM Serial MMIO configuration
* Revert previous commit & reintroduce ARM64 cache functions
* Add ACPI MCFG Table description & SMP parsing. This requires careful review/testing to avoid BC issues!
* Revert previous commmit and reintroduce relocation and heap change for ARM64
* ARM64 does not support CPU PNS. Use DMI type4 parsing instead. Add SMBIOS v3 support (ARM64 does not support v2)
* Fix typo in pci.h
* Move Aarch64 load-limit computation from main.c to pmem.c
* Add .arm64 to version string. Use PMU for clock computation display. Fix D5 Temp NULL not handled
* Add Makefile and linker scripts for aarch64. Set cross-compiler from x86 by default
* Attempt to add aarch64 to workflow
* Remove a remaining internal debug flag
* Correct typos
* Fix ARM64 SMP freeze
assign heap when RAM is one contiguous region, keep it below 3GB for DMA (RPi5), add DSB before SEV to avoid missed barrier wakeups
Sync I-cache with D-cache after program relocation to prevent stale instruction fetch
* Validate MADT entry lengths to avoid reading past the table (or looping forever) on malformed ACPI tables
* aarch64: add NEON kernels for the vector PRSG tests
Tests 3 (bus stress) and 5 (moving inversions, random) now dispatch to 128-bit NEON fill/scan instead of scalar.
* Fix ARM64 data abort from the per-second DMI check & fix unbounded strstr()
* Fix ARM64 data abort when saving results to USB after a relocation
* Update README.md with AArch64 (ARM64) support
* aarch64: shrink static string tables, harden MCFG/paging
Replace pointer-based name tables with inline char arrays (saves ~1.5KB + relocs)
alidate MCFG length/bus ranges, and bound pm_map/vm_map fills against overflows
* Add NVIDIA & latest Apple ARM SoC to cpuid.c
* Fix stale pointers read by the report writer after a program relocation
cpu_model gets a static init (creates its reloc record)SPD type becomes an inline char array
* Initial commit for USB Mass Storage Support
* Add support for SCSI_16 and various fixes by debrouxl
* Fix USB HCD registration to skip failed probes (when a mass storage device was already found)
* Fix xHCI bulk transfer completion matching & accept short packets for IN transfers
* Add USB BOT error recovery and match xHCI control events by slot/EP
* Add EHCI bulk timeout/size guard, fix per-controller MSD port handling, and make xHCI keyboard re-arm precise
* Harden FAT/GPT parsing (cluster validation & block-size check) and fix RTC read issue due to R/W race
* Fix report varargs on x86_64, truncate F6 drive label, and clean up failed FAT file writes
* Fix stale hub VID/PID read, refactor USB MSD detection to helper & tidy usbhcd/display/config layout
* Scan for USB drives on demand when saving a report
Keep EHCI/xHCI controllers registered when empty and rescan free root ports on F6.
Also fix xHCI keyboard re-arm losing a key release, dropping the next same-key press.
* Display memory info from DMI when SPD is unavailable
* ARM64 does not support CPU PNS. Use DMI type4 parsing instead. Add SMBIOS v3 support (ARM64 does not support v2)
* Hardened AP Stack Management (see PR for details)
* Fix low-memory boot issues caused by the larger AP stack area
Zero only _bss.._stacks at first boot (the full sweep wiped ACPI/SMBIOS anchors above 0xE0000 on writable-shadow platforms), verify relocation addresses against pm_map, and relocate before smp_start() when the enabled CPUs' stacks would extend beyond usable low RAM, setting up the AP trampoline at start time.
Blacksmith-style non-uniform, REFRESH-synchronised many-sided hammering with DRAMA-lite row-stride discovery and a blind-stride fallback
x86 clflush(opt) engine with a coarse whole-cache-flush fallback for other targets. LA64 TBT
Replace tests 5 & 8 with a single moving inversions test using per-lane
xorshift sequences and non-temporal stores. Kernels (inline asm) are picked
at runtime via the new system/simd module: AVX2, SSE2 or scalar, with the
tier shown in the test name.
Fix and enable the AVX/XCR0 startup code and decode the XSAVE/AVX/AVX2 CPUID flags.Suite shrinks from 11 to 10 tests.
Adds external L2 cache size detection for Socket 7 boards with SiS 530
northbridge, and extends the existing ALi quirk to also cover Aladdin IV
(M1531) in addition to Aladdin V (M1541).
Tested on: K6-II + SiS 530 with 512KB L2 cache.
Closes#602
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Enable SSE2 on x86_64 build
* Better Memory Bandwidth measurement
- Moved memory speed measurement to a dedicated file
- Use SSE2 on x86_64 for better DRAM BW measurements
- Add a lot of safeguards to avoid issue with very large L3 cache
- Add a more precise way to target a specific cache
- Change the iteration number from fixed to time-constrained so overall test time is always same
- Added many configuration parameters for fine-tuning
* Revert saving XMM registers to stack.
Instead, make sure to use only GPR for interrupt handling (so it won't touch SIMD regs)
* system/loongarch: Decode CPU temperature as signed 8-bit
Interpret the low 8 bits of the CPU temperature register as a signed
value, apply the platform-specific offset, and reject readings when the
temperature-valid bit is clear.
At low temperatures the raw register value would otherwise be interpreted
as a large positive number, which breaks the displayed reading.
Reported-by: Mingcong Bai <jeffbai@aosc.io>
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* Better display of CPU temp from -99°C to 999°C
* Add sentinel value for CPU_TEMP_INVALID to allow negative temperature
---------
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* First commit to support x2APIC
* Keep apio_x2apic bool everywhere to avoid compilation issues on LA64.
x2APIC support on LA64 must be checked later (probably different MSRs)
* Various fixes
- Fix flags in MADT x2APIC (CPU only has ENABLED, not ONLINE
- Increased chunk index and related function from 8 to 16-bit
- Increase MAX_APS and MAX_APIC_IDS to 512 (need an APs stack size evaluation to be sure we will not overflow)
On LoongArch, PCIe MMIO space above 4 GiB must be mapped as uncached;
otherwise writes may not reach the device, so framebuffer updates are not visible.
Adjust the PCIe memory window layout according to the Loongson 2K series documentation.
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Unlike x86_64 where rep movsl/movsq could be turned into efficient uOP
to achieve a good performance, on LoongArch a simple loop that copies
only 8 bytes per iteration couldn't fully feed the pipeline.
This makes calculated cache bandwidth suspcious: on my Loongson 3A5000
laptop, memtest86plus reports the same bandwidth for L1 and L2, which is
obviously incorrect.
Let's unroll memspeed loop to copy 64-bytes per iteration, which fits
in a cacheline and should fully feed the pipeline for even future
generations of Loongson cores.
Signed-off-by: Yao Zi <me@ziyao.cc>
* Recognise VT52/VT100/VT220 key escape sequences on serial console.
Map function keys to '0' to '9' and cursor keys to 'u', 'd', 'l',
'r', as is done for legacy and USB keyboards. Ignore all other
special key sequences.
* Make serial_echo_print() and tty_goto() static.
These are local to serial.c. Making them static saves a few bytes.
* Update keyboard.h to document cursor key mapping.
* Added some escape codes for terminals & VT100+
Change input order to check TTY first
* Replace comments about PF6-10
---------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Initial commit for DDR5 Temperature report
* Change smbus.h to i2c_x86.h
* Change I2C includes defines name to avoid conflict
* Add dummy get_ram_temp() function on LA64
* Add menu option for RAM/DDR5 Temperature polling
* Add USB hub quirk to support AMI virtual keyboard (issue #523)
From testing it appears that the AMI virtual devices do not work
correctly if you disable one port on the virtual hub then reuse the
USB address for a device connected to another port on that hub. So
add a quirk to detect the virtual hub from its vendor/product ID
and leave all ports on that hub active when performing the scan for
USB keyboards. This will permanently reserve a bit more memory, but
not significantly so.
* Replace hard-coded USB vendor ID with macro definition.
* Update Intel i801 PCI device IDs list from the Linux driver.
* Add support for MTL-P (eg: NUC 14th Gen)
---------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
The usbdebug option may now be optionally followed by "=hub" or "=kbd",
which enables details of the configuration and endpoint descriptors to
be printed when scanning for hubs or keyboards respectively. This can
easily result in more than one screenful of information (and we can't
say "press any key to continue" before we've completed the scan and set
up the keyboard handler), so a 1 second delay is added after printing
each line of detailed information.
* loongarch: adjust 2K/3B6000M DDR rate factor
* loongarch: Supports fewer cache layers than L3
For example: 2K2000 chip does not have L3, but has L2.
If L2Cache is not flushed to memory, it will cause read and write data errors after cache_off.
If a legacy BIOS has enabled PS/2 mouse input, the bytes received on
port 0x60 may come from either the keyboard or the mouse. Currently
we treat all bytes as keyboard input, which means mouse input will be
translated into arbitrary key codes. This may cause a memory test to
be interrupted or aborted. We should instead disable or ignore any
mouse input.
Although it should be possible to reconfigure the PS/2 controller to
disable mouse input, it's quite likely that there's some quirky H/W
out there that makes this more complicated than it seems. The simple
solution is to detect mouse input by checking whether bit 5 of the
received byte is set and discarding it if so.
Currentilly, it only compares the root bus DID is 0x7A00 which sometimes
fails, a new logic was added to compare the 7A2000 EHCI DID to fix it.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/loongarch: Add 64-bit PCIe memory space mapping
Added the 64-bit PCIe memory space mapping. From 0x8000000000ULL to
0xFD00000000ULL are LoongArch 64-bit PCIe memory spaces and need to be
mapped.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/loongarch: Optimization timer on LoongArch
Since some LoongArch64 CPUs stop the performance counters when ilde, the
running time displayed on the screen is incorrect.
Using stable counter can solve this problem, so remove the performance
counters time, and add stable counter time.
Signed-off-by: Chao Li <lichao@loongson.cn>
---------
Signed-off-by: Chao Li <lichao@loongson.cn>
Lionel Debroux
Sam Demeulemeester
Sam Demeulemeester
Nikolaos Barkas
Dongyan QianandSam Demeulemeester
Jonathan Teh
Yao Zi
martinwhitakerandSam Demeulemeester
David Corvaglia
Chao Li