* cpuinfo: Fix WinChip and Cyrix/NSC CPU name and cache info
Always populate the cache info from extended CPUID, it is not used for
Intel CPUs, even though it is present, and is useful for non-Intel CPUs.
Fix the CPU name and cache sizes for Centaur and Cyrix/NSC CPUs without
brand string, which are the WinChip C6 and all Cyrix CPUs except the
Media GXm.
For the Media GXm and Geode GXm/GXLV/GX1, which are available with both
Cyrix and NSC vendor strings, hardcode the L1 cache size. The Geode GX2
uses standard cache info.
* Add 'Intel' in CPU names for older CPUs
* Add 'Transmeta' and 'IDT' in CPU names for older CPUs
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Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Support cache and temperature info for VIA/Centaur/Zhaoxin CPUs
Use extended CPUID for VIA C3/C7/Nano cache information.
Use MSR reads for Nano/Zhaoxin and VIA C7 processor temperature.
Tested on VIA C7-D 1.5GHz.
* Small code conventions fixes
* Fix overallocation of cpuid_cache_info_t union (From PR #263)
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Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Improve abstraction in vmem.h and limit memory benchmarking to first 2GB.
The third GB may get used for remapping memory regions that are only
accessed during startup, so it's not safe to use it for the memory
speed tests.
* Fix calculation of end limit for locating memory benchmark workspace.
* Document vmem.h.
* Use window number, not current start address, to detect first window.
* Increase the program low-load range from 1MB to 4MB and make more robust.
If the BIOS has reserved some parts of low memory, there may not be
enough contiguous space left to load the program there (issue #49).
So increase the low-load range to include the first 3MB of high
memory. Also guard against the program being initially loaded
straddling the new boundary.
Co-authored-by: Martin Whitaker <memtest@martin-whitaker.me.uk>
