TODO:
* selective NX enablement on pd0, pd1 and pd3.
Unconditional NX on the whole pd3 makes memtest86+ reboot in a QEMU-emulated computer.
* if supported on all x86_64 CPUs, simply enable long mode and NX simultaneously ? A real K8 dual-core processor didn't seem to hate it, at least.
* startup code: NX enablement for x86, on capable computers (CPUID 0x80000001, edx bit 20).
* set the appropriate flag in the headers.
Adds external L2 cache size detection for Socket 7 boards with SiS 530
northbridge, and extends the existing ALi quirk to also cover Aladdin IV
(M1531) in addition to Aladdin V (M1541).
Tested on: K6-II + SiS 530 with 512KB L2 cache.
Closes#602
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Enable SSE2 on x86_64 build
* Better Memory Bandwidth measurement
- Moved memory speed measurement to a dedicated file
- Use SSE2 on x86_64 for better DRAM BW measurements
- Add a lot of safeguards to avoid issue with very large L3 cache
- Add a more precise way to target a specific cache
- Change the iteration number from fixed to time-constrained so overall test time is always same
- Added many configuration parameters for fine-tuning
* Revert saving XMM registers to stack.
Instead, make sure to use only GPR for interrupt handling (so it won't touch SIMD regs)
* system/loongarch: Decode CPU temperature as signed 8-bit
Interpret the low 8 bits of the CPU temperature register as a signed
value, apply the platform-specific offset, and reject readings when the
temperature-valid bit is clear.
At low temperatures the raw register value would otherwise be interpreted
as a large positive number, which breaks the displayed reading.
Reported-by: Mingcong Bai <jeffbai@aosc.io>
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* Better display of CPU temp from -99°C to 999°C
* Add sentinel value for CPU_TEMP_INVALID to allow negative temperature
---------
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* First commit to support x2APIC
* Keep apio_x2apic bool everywhere to avoid compilation issues on LA64.
x2APIC support on LA64 must be checked later (probably different MSRs)
* Various fixes
- Fix flags in MADT x2APIC (CPU only has ENABLED, not ONLINE
- Increased chunk index and related function from 8 to 16-bit
- Increase MAX_APS and MAX_APIC_IDS to 512 (need an APs stack size evaluation to be sure we will not overflow)
On LoongArch, PCIe MMIO space above 4 GiB must be mapped as uncached;
otherwise writes may not reach the device, so framebuffer updates are not visible.
Adjust the PCIe memory window layout according to the Loongson 2K series documentation.
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
Unlike x86_64 where rep movsl/movsq could be turned into efficient uOP
to achieve a good performance, on LoongArch a simple loop that copies
only 8 bytes per iteration couldn't fully feed the pipeline.
This makes calculated cache bandwidth suspcious: on my Loongson 3A5000
laptop, memtest86plus reports the same bandwidth for L1 and L2, which is
obviously incorrect.
Let's unroll memspeed loop to copy 64-bytes per iteration, which fits
in a cacheline and should fully feed the pipeline for even future
generations of Loongson cores.
Signed-off-by: Yao Zi <me@ziyao.cc>
* Recognise VT52/VT100/VT220 key escape sequences on serial console.
Map function keys to '0' to '9' and cursor keys to 'u', 'd', 'l',
'r', as is done for legacy and USB keyboards. Ignore all other
special key sequences.
* Make serial_echo_print() and tty_goto() static.
These are local to serial.c. Making them static saves a few bytes.
* Update keyboard.h to document cursor key mapping.
* Added some escape codes for terminals & VT100+
Change input order to check TTY first
* Replace comments about PF6-10
---------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
* Initial commit for DDR5 Temperature report
* Change smbus.h to i2c_x86.h
* Change I2C includes defines name to avoid conflict
* Add dummy get_ram_temp() function on LA64
* Add menu option for RAM/DDR5 Temperature polling
* Add USB hub quirk to support AMI virtual keyboard (issue #523)
From testing it appears that the AMI virtual devices do not work
correctly if you disable one port on the virtual hub then reuse the
USB address for a device connected to another port on that hub. So
add a quirk to detect the virtual hub from its vendor/product ID
and leave all ports on that hub active when performing the scan for
USB keyboards. This will permanently reserve a bit more memory, but
not significantly so.
* Replace hard-coded USB vendor ID with macro definition.
* Update Intel i801 PCI device IDs list from the Linux driver.
* Add support for MTL-P (eg: NUC 14th Gen)
---------
Co-authored-by: Sam Demeulemeester <github@x86-secret.com>
The usbdebug option may now be optionally followed by "=hub" or "=kbd",
which enables details of the configuration and endpoint descriptors to
be printed when scanning for hubs or keyboards respectively. This can
easily result in more than one screenful of information (and we can't
say "press any key to continue" before we've completed the scan and set
up the keyboard handler), so a 1 second delay is added after printing
each line of detailed information.
* loongarch: adjust 2K/3B6000M DDR rate factor
* loongarch: Supports fewer cache layers than L3
For example: 2K2000 chip does not have L3, but has L2.
If L2Cache is not flushed to memory, it will cause read and write data errors after cache_off.
If a legacy BIOS has enabled PS/2 mouse input, the bytes received on
port 0x60 may come from either the keyboard or the mouse. Currently
we treat all bytes as keyboard input, which means mouse input will be
translated into arbitrary key codes. This may cause a memory test to
be interrupted or aborted. We should instead disable or ignore any
mouse input.
Although it should be possible to reconfigure the PS/2 controller to
disable mouse input, it's quite likely that there's some quirky H/W
out there that makes this more complicated than it seems. The simple
solution is to detect mouse input by checking whether bit 5 of the
received byte is set and discarding it if so.
Currentilly, it only compares the root bus DID is 0x7A00 which sometimes
fails, a new logic was added to compare the 7A2000 EHCI DID to fix it.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/loongarch: Add 64-bit PCIe memory space mapping
Added the 64-bit PCIe memory space mapping. From 0x8000000000ULL to
0xFD00000000ULL are LoongArch 64-bit PCIe memory spaces and need to be
mapped.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/loongarch: Optimization timer on LoongArch
Since some LoongArch64 CPUs stop the performance counters when ilde, the
running time displayed on the screen is incorrect.
Using stable counter can solve this problem, so remove the performance
counters time, and add stable counter time.
Signed-off-by: Chao Li <lichao@loongson.cn>
---------
Signed-off-by: Chao Li <lichao@loongson.cn>
In LoongArch, the addresses from 0x30000000 to 0x80000000 are 32-bit PCI
memory space, If the BAR happens start at 0x30000000, a mapping error
will occur according to the old logic, and 0x30000000 should also be
mapped, so fix it.
Signed-off-by: Chao Li <lichao@loongson.cn>
* Add CPUID detection for MTL & ARL CPUs
* Add support for ARL SMBus Controler
Add PCI Device polling on Bus 0x80 (instead of fixed 0x00)
Solve issue with DDR5 SPD Bank switching when SPD Write is disabled (using Proc Call)
* Add Live Freq/Timings IMC Polling for Intel MTL & ADL CPUs
* Correct K8 Rev G detection
Fix#361 (PR hijacking)
* lib/assert: Add LoongArch assert support
Added LoongArch break 3 assert instruction.
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/barrier: Add barrier method for LoongArch
Added LoongArch barriers in barrier_spin_wait and barrier_halt_wait
functions.
Signed-off-by: Chao Li <lichao@loognson.cn>
* lib/spinlock: Add LoongArch CPU pause
Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/string: Make LoongArch use the string function in the file
Since LoongArch GCC doesn't have built-in string functions, use the
string function instance in the sting.c
Signed-off-by: Chao Li <lichao@loongson.cn>
* lib/unistd: Add LoongArch CPU pause
Because the LoongArch haven't pause instruction, using eight nops to
replace the pause.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/acpi: Reduce the way of search RSDP for non-x86 ARCHs
Searching RSDP from legacy BIOS EDBA and reserved areas is available
only on i386 and x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/cache: Add LoongArch64 cache operations support
Added cache operations support for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/cpuid: Add the compile limit
Make the `cpuid` function action only on i386/x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/heap: Add heap support for LoongArch64
LoongArch64 uses the low 256MB as the low memory.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/memrw: Add 8-bit and 16-bit memory operations
Added 8-bit and 16-bit memory access operations, which 8-bit uses
`movb` and 16-bit is `movw`.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/memrw: Add LoongArch memory access operations
Added 8/16/32/64-bit memory access operations for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add Loongson PCI vendor ID and Loongson 7A chipset EHCI workaround
1. Added Loongson PCI vendor ID.
2. Added Loongson 7A chipset ECHI workaround.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/io: Add LoongArch64 IO port operations
Added IO port operations for LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/reloc64: Add LoongArch64 relocations support
Added R_LARCH_RELATIVE and R_LARCH_NONE relocations support for
LoongArch64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/serial: Add Loongson CPU serial port support
Add the serial port address perfix of Loongson CPU and obtain serial
port clock method.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/smbus: Rename smbus.c to i2c_x86.c
Renamed the smbus.c to i2c_x86.c in i386 and x64 platforms.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/smp: Add LoongArch SMP support
Added LoongArch multi-core support and a way of map to node numbers if
the NUMA is enabled.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/timers: Add LoongArch supports
In LoongArch, there is a stable counter that is independent of other
clocks, it like the TSC in x64. Using it to count the ticks per
millisecond.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/tsc: Add LoongArch support
Usually the frequency of stable counter is not same to CPU frequency, so
using the performance counter for the delay operations.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/usbhcd: Add LoongArch MMIO perfix
Added LoongArch64 MMIO address perfix, use for address the PCI memory
space.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/usbhcd: Add Loongson 7A2000 chipset OHCI BAR offset fix
If the BAR address is not fixed for the Loongson 7A2000 OHCI controller,
some prots will not be usable, This change currently only affects the
LoongArch platform.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add the way to IO access via MMIO
Usually, it is access the IO like PCI IO via MMIO on non-X86 ARCHs, so
a method to access IO via MMIO is added.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system: Add the way to access PCI memory space via MMIO
Some uniformly address ARCHs access the PCI memory depended the MMIO, so
the method to access PCI memory via MMIO is added.
Signed-off-by: Chao Li <lichao@loongson.cn>
* app: Add LoongArch version support
Reduced the version field by two characters to support ARCH name
abbreviations with more than three characters, and added "la64" ARCH
version display.
Singed-off-by: Chao Li <lichao@loongson.cn>
* test/block_move: Add block move test via ASM for LoongArch
Add block move test inline assembly instance for LoongArch.
Signed-off-by: Chao Li <lichao@loongson.cn>
* test/mov_inv_fixed: Add LoongArch ASM version word write operation
Add LoongArch ASM version word write cycle if it uses the HAND_OPTIMISED.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot: Adjust the AP stack size for LoongArch
LoongArch exception will store all of the GP, FP and CSR on stack, it
need more stack size, make LoongArch AP using 2KB stack size.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot/efisetup: Add LoongArch CPU halt instruction
Add "idle 0" for LoongArch
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot/efi: Limiting the ms_abi using scope
Make the ms_abi only work on i386 and x64.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/imc/loongson: Add Loongson LoongArch IMC support
Added the Loongson LoongArch CPU IMC instance, support read out the IMC
sequence, currently only supports reading MC0.
Signed-off-by: Chao Li <lichao@loongson.cn>
* app/loongarch: Add intrrupt handler for LoongArch
Added the LoongArch IRQ handler support.
Signed-off-by: Chao Li <lichao@loongson.cn>
* system/loongarch: Add LoongArch ARCH specific files
Added LoongArch ARCH specific files: cpuid.c, cpuinfo.c, hwctrl.c,
memctrl.c, temperature.c, vmem.c, registers.h
They use the same pubilc API for i386 and x64 platforms.
Signed-off-by: Chao Li <lichao@loongson.cn>
* boot: Add LoongArch startup and header
Added the header.S and startup64.S for LoongArch, CPU works on:
1. Page mode.
2. Load and store is cacheable.
3. Instructions is cacheable.
4. DMWn 0 and 1 is used.
5. To access non-cacheable areas, use the perfix 0x8000000000000000.
Signed-off Chao Li <lichao@loongson.cn>
* build64/la64: Add LoongArch64 build files
Add infrastructure files to build memtest86 plus for LoongArch64
platform.
Signed-off-by: Chao Li <lichao@loongson.cn>
* workflows: Add LoongArch64 CI supports
Adjust workflow logci, remvoe 32 and 64 wordsize, replace with "i386,
x86_64 and la64", add LoongArch64 build CI check.
Signed-off-by: Chao Li <lichao@loongson.cn>
---------
Signed-off-by: Chao Li <lichao@loongson.cn>
Signed-off-by: Chao Li <lichao@loognson.cn>
* Split SPD parsing and printing code from smbus.c to spd.c
Move all SPD parsing and printing code from smbus.{c,h} to spd.{c,h}.
Introduce parse_spd() function, moving the parse_spd_* selection logic
from print_smbus_startup_info(), allowing to keep parse_spd_* static.
Remove static from get_spd() and update print_smbus_startup_info()
to use parse_spd() which also simplifies the code flow.
Move LINE_SPD into display.h and rename it to ROW_SPD. Update print_spdi()
to use explicit row number where the SPD info needs to be printed.
Rename ram_info into ram_info_t, rename print_smbus_startup_info()
into print_spd_startup_info.
Do not initialize ram.freq to 0, this is the initial value already.
Do not set curspd.isValid to False, the first thing that parse_spd()
does is setting the entire struct to 0, that also sets isValid to False.
print_spd_startup_info() from smbus.c is technically a skeleton now
so each arch can have its own version, adjusted as needed. Once
LA64 changes land, we can think how we can even make it arch agnostic.
* Add -fexcess-precision=standard to CFLAGS for build(32,64)/Makefile
Recent switch from -std=c11 to -std=gnu11 done in 53ca89f ("Add
initial NUMA awareness support") introduced a regression in SPD
parsing code (and potentially in other places) due to change of
floating point precision. Restore the original behavior by
adding -fexcess-precision=standard to CFLAGS.
Bug: https://github.com/memtest86plus/memtest86plus/issues/425
Fixes: https://github.com/memtest86plus/memtest86plus/commit/53ca89f8aeeea649a1b8c2d2d14ec121f7025f54
Added a new CC flag into build32 and build64 Makefiles to distinguish
whether compiling to 32-bit or 64-bit code.
[Lionel Debroux: rebased on the memrw functions refactor.]
Signed-off-by: Chao Li <lichao@loongson.cn>
The existing algorithm both read and wrote data beyond the end of the
array and, when moving data, moved it in the wrong direction. Replace
it with a bog-standard insertion sort algorithm. The resulting code
is smaller and probably faster, as memmove() is not in-lined.
Lionel Debroux
Sam Demeulemeester
Nikolaos Barkas
Sam Demeulemeester
Dongyan QianandSam Demeulemeester
Jonathan Teh
Yao Zi
martinwhitakerandSam Demeulemeester
David Corvaglia
Chao Li
01e3