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Author SHA1 Message Date
Sam Demeulemeester 70e4ec1881 Add support for 100+ new DRAM vendors & update JEP106 list 2026-10-06 17:59:40 +02:00
Sam Demeulemeester bf9dff4632 Document AArch64 support status on README.md 2026-10-06 16:14:31 +02:00
Sam Demeulemeester 6c28a985bc imc/mtl: read timings from CH1 when CH0 is unpopulated 2026-10-06 14:56:00 +02:00
Sam Demeulemeester 3334d7296a Fix failed read on SPD5 Hub due to incomplete previous write 2026-09-08 14:45:45 +02:00
Sam Demeulemeester ed5770abfa Add proper cache detection for Transmetta CPUs 2026-09-08 14:45:45 +02:00
Sam Demeulemeester ccbac76118 Fix swapped L1D/L1I on CPUID 0x8000005 decoding 2026-09-08 14:45:45 +02:00
Sam Demeulemeester 48cdcffb9e Generate .sbat from sbat_csv.h so the version tracks MT_VERSION 2026-09-08 14:45:45 +02:00
Sam Demeulemeester e78311db5a i2c: add support for Intel Wildcat Lake SoC (tested working) 2026-09-08 14:45:45 +02:00
Sam Demeulemeester 1e556aec7c aarch64: fix SMBIOS parsing crash when loaded via shim 
map startup-only regions as Normal memory
 2026-09-08 14:45:45 +02:00
Sam Demeulemeester a520744ac9 Fix direct shim loading due to zero-padded sbat section 
use exact .sbat VirtualSize, section moved last (regressed by .osrel in dae548f)
Remove dead .bss-clear debug code from efi_handover (shim-review)
 2026-09-08 14:45:45 +02:00
Sam Demeulemeester 20e6302cca Fix dead PS/2 KBs on AT-class 8042 controllers (ie: MSI MS-6167) 
Since e285fbb ('Ignore PS/2 mouse events') every scancode was discarded as a
mouse event: AT-class KB Controllers set status bit 5 as a transmit timeout,
not AUX data. Only honour the filter when the config byte enables AUX.
 2026-09-08 14:45:45 +02:00
Sam Demeulemeester 269fbcceea Fix save-to-USB fails after drive hotplug or replug 
Validate the cached MSD and rescan if stale, detect a replug via CCS+PED on xHCI,
retry msd_init once via port-reset re-enumeration, clear unit attention with REQUEST SENSE
 2026-09-08 14:45:45 +02:00
Sam Demeulemeester e18aa349ff USB: relocate BARs left unassigned or in DRAM-decoded space by the BIOS 
Add pci_alloc_mmio() on x86; retry first GET_DESCRIPTOR on stalling drives
 2026-09-08 14:45:45 +02:00
Sam Demeulemeester 568e471c3d Use the git commit date for fallback FAT timestamps to keep builds reproducible (shim-review) 2026-09-08 14:45:45 +02:00
Sam Demeulemeester 3942d25f2a Add FAT file timestamps to USB report saving (RTC on x86, build date elsewhere) 2026-09-08 14:45:45 +02:00
Sam Demeulemeester 306bcd0659 EHCI: don't give up on BIOS handoff timeout 
On any init failure, clear CONFIGFLAG so ports revert to companion HCs
 2026-09-08 14:45:45 +02:00
Sam Demeulemeester a04347dddd Improve USB mass storage reliability on legacy EHCI/UHCI systems 
EHCI: don't treat the qTD Ping State bit as an error, disable SMIs at BIOS
handoff, fail fast and recover when the controller halts, and stop DMA before
freeing controller memory (also on UHCI).
 MSD: retry failed BOT commands.
FAT32: cache the current sector.
Quirk: fix VIA VT823x EHCI bus starvation.
 2026-09-08 14:45:45 +02:00
Sam Demeulemeester f9ab5e36cf Fix L3 cache size on AMD Asymmetric Dual-CCD CPUs 2026-07-20 13:57:56 +02:00
Sam Demeulemeester 6789cd5148 Fix random SMP hangs in x2APIC mode by fencing the ICR write 
WRMSR to the x2APIC MSRs is not serializing, so an IPI could be sent
before older stores (eg: the barrier wakeup flags) are globally visible,
deadlocking the woken CPU on stale data.

Insert MFENCE;LFENCE before the ICR write, as required by the
Intel SDM (vol 3A, 11.12.3) and matching the linux kernerl
weak_wrmsr_fence(). The need for lfence is mostly black magic...
 2026-07-19 17:16:21 +02:00
Sam Demeulemeester 0738fdd2a0 Replace JEDEC code/pointer pairs with a code array + string table, saving 172 relocations and a few KB. 
Suggested-by: Lionel Debroux <lionel_debroux@yahoo.fr>
Suggested-by: 01e3 <01e3@ans.pl>
 2026-07-13 07:26:46 +02:00
Sam Demeulemeester 2dc40e0885 Add System/MB Serials to USB Report. Remove disabled tests 2026-07-12 23:55:07 +02:00
Sam Demeulemeester 115b98e922 Fix hang when the BSP is NOT the first CPU listed in the MADT 
Find the boot CPU's APIC ID in the table and move it to slot 0, otherwise
smp_start() sends INIT-SIPI to the BSP itself and hangs the system.
Also skip entries whose APIC ID is already listed, as some firmwares
declare the same core as both a local APIC and an x2APIC entry.
This is a strict violation of the ACPI specs, but it happens...
 2026-07-12 20:02:16 +02:00
Sam Demeulemeester d105c55e15 Normalize membw.c to LF and enforce LF endings via .gitattributes 2026-07-12 18:30:19 +02:00
Sam Demeulemeester 951cd58833 benchmark: account for RFO traffic in cached copies (fixes L3 speed too low) 2026-07-12 18:29:04 +02:00
Sam Demeulemeester c21e2cfa00 Move bus stress test from test 9 to test 3 to minimise time to first fault 2026-07-11 11:22:01 +02:00
Sam Demeulemeester 80717a1c5b Invert the PRSG xorshift stages by repeated squaring (~25% faster) 2026-07-11 11:22:01 +02:00
Sam Demeulemeester 72d08688ba Add rowhammer test (new test 11), disabled by default 
Blacksmith-style non-uniform, REFRESH-synchronised many-sided hammering with DRAMA-lite row-stride discovery and a blind-stride fallback
x86 clflush(opt) engine with a coarse whole-cache-flush fallback for other targets. LA64 TBT
 2026-07-11 11:22:01 +02:00
Sam Demeulemeester eaeaff181b Add bus stress test with fine-grained R/W turnarounds (new test 9) 
Two per-CPU streams alternate NT-store bursts of a fresh PRSG sequence with read-verify of the previous round, forcing write-to-read turnarounds and row conflicts; odd rounds insert idle gaps to provoke PMIC load steps. Targets DDR5-era interface faults (link SI, marginal XMP/EXPO training, voltage droop) that on-die ECC cannot correct
Moving PRSG vector kernels from mov_inv_rng.C to a shared module in tests/
 2026-07-11 11:22:01 +02:00
Sam Demeulemeester 6639e5cfb8 Enhance bit fade test: solid + random rounds (4 x 120s), parallel fill/check 2026-07-11 11:22:01 +02:00
Sam Demeulemeester 7f281dc670 Slightly adjust test dispatch (NT Store faster than expected 2026-07-11 11:22:01 +02:00
Sam Demeulemeester 55d4508adc Reorder tests and rebalance iterations to reduce time-to-first-fault 
Run the random sequence test (now #4) and Modulo-20 (now #6) before the 64-bit shifting pattern test (now #8), so that every fault class is probed early in the pass.
Trade the walker's redundant repetitions (3 -> 1 iteration, plus only every other offset on the fast first pass) for more never-repeating work (random sequence 24 -> 96 rounds, Modulo-20 6 -> 9), at unchanged pass time.
 2026-07-11 11:22:01 +02:00
Sam Demeulemeester 4e76e517eb Add SIMD moving inversions test with random sequences (AVX2/SSE2) 
Replace tests 5 & 8 with a single moving inversions test using per-lane
xorshift sequences and non-temporal stores. Kernels (inline asm) are picked
at runtime via the new system/simd module: AVX2, SSE2 or scalar, with the
tier shown in the test name.
Fix and enable the AVX/XCR0 startup code and decode the XSAVE/AVX/AVX2 CPUID flags.Suite shrinks from 11 to 10 tests.
 2026-07-11 11:22:01 +02:00
Sam Demeulemeester 7ff45d9466 Early version bump to v9.00 2026-07-07 16:40:42 +02:00
Sam Demeulemeester ffe3890502 Add acknowlegdment for LA64 port in README.md 2026-07-07 16:39:56 +02:00
Sam Demeulemeester 997d4d2da2 Suppress GCC 12+ warnings from BIOS Direct Access 2026-05-22 15:34:56 +02:00
Sam Demeulemeester 494689a7ac Add many JEDEC IDs for unknown DRAM manufacturers 2026-05-06 22:25:51 +02:00
Sam Demeulemeester f0ae889c7e Make Invalid Temperature Sentinel Agnostic 
Do not display DDR5 Temperature when not available
 2026-04-07 18:52:38 +02:00
Sam Demeulemeester 7eb2568dfe Add support for Intel Lunar Lake & Panther Lake CPUs 2026-03-23 17:52:55 +01:00
Sam Demeulemeester a90edd63ce Fix tRP measurement on Intel LPDDR5 laptop 
Use tRPpb instead of tRPab
 2026-03-23 17:52:02 +01:00
Sam Demeulemeester 82bb87a710 Early bump to v8.10 2026-03-17 00:37:45 +01:00
Sam Demeulemeester e486dde638 Fix shadowed var declaration and whitespaces issues in config.c 2026-03-17 00:37:18 +01:00
Sam Demeulemeester feeb7d2d01 Fix Core Topology Determination on some CPUs (eg: Intel PTL) 2026-03-17 00:15:46 +01:00
Sam Demeulemeester 6af76b804b Enable DDR5 Temperature polling 2025-10-07 15:38:27 +02:00
Sam Demeulemeester ac7d092417 Added various DRAM manufacturers from JEP106 list 
Manually reworked strings
 2025-10-05 16:26:58 +02:00
Sam Demeulemeester 6888b1d5a0 Add support for Intel Arrow Lake-H (SOC) 
Tested OK on NUC 15th Gen.
 2025-10-05 16:02:07 +02:00
Sam Demeulemeester 2f9b165eec Add support for AMD Hawk Point FP7 (Phoenix) 2025-05-27 22:02:41 +02:00
Sam Demeulemeester 4d08b14a3d Remove Ubuntu 20.04 from workflows due to deprecation 2025-04-20 19:22:33 +02:00
Sam Demeulemeester a47b2bc053 Fix DDR5 SPD parsing issue for XMP 3.0 frequency 
On DDR5, limit XMP profile parsing to 2 to avoid conflict between XMP and EXPO
Add a check to skip very low tCK values
 2025-04-20 19:16:51 +02:00
Sam Demeulemeester 3b1d85291d Change README.md to add recently added 'dark' mode 2025-02-10 23:39:13 +01:00
Sam Demeulemeester b51c6e75f3 Add Thermaltake and SSTC Jedec IDs 2025-01-27 19:41:36 +01:00
Sam Demeulemeester a65857b702 Early bump to v8.00 2025-01-27 19:28:03 +01:00
Sam Demeulemeester 5a046291fa Add a few RAM manufacturers in JEDEC DB 2024-11-12 00:25:38 +01:00
Sam Demeulemeester 52c6c64d57 Bump version to v7.20 2024-11-11 15:28:41 +01:00
Sam Demeulemeester 46e3b43859 Add support for latest AMD Zen5 CPU (Ryzen 9000) 
Change DDR5 SPD Bank switch method on AMD according to feedbacks from betatesters
 2024-11-10 23:45:49 +01:00
Sam Demeulemeester 2d3b14ed1a Add detection for various JEDEC Manufacturers 2024-01-07 15:20:19 +01:00
Sam Demeulemeester fc2826726b Early Bump to v7.00 
Requested by many betatesters due to the amount of changes since 6.20 release
ECC support for a few platforms planned before v7.00 release
 2023-08-06 20:33:30 +02:00
Sam Demeulemeester 10782c2aad Remove HOW_TO_DEBUG_WITH_GDB.md from root 2023-08-06 20:28:57 +02:00
Sam Demeulemeester 555908137e Move HOW_TO_DEBUG_WITH_GDB.md to doc/ 2023-08-06 17:28:16 +02:00
Sam Demeulemeester 03b6cbe4e4 Add IMC polling for AMD Rembrandt 
Refactor cpuinfo() for AMD Family 19h CPUs and add detection for AMD Chagall, Storm Peak, Rembrandt, Phoenix and Granite Ridge
 2023-06-01 22:00:02 +02:00
Sam Demeulemeester de4f4768fc Fix various temperature-related issues on older Atom CPUs 
Also, remove the no_temperature var to keep only the enable_temperature flag
Older Atom still have the enable_temperature flag hard-coded to false until further tests are done
 2023-05-18 16:03:48 +02:00
Sam Demeulemeester 5dcd424ea7 Bump version to v6.20 2023-05-07 16:55:03 +02:00
Sam Demeulemeester 1f1fe5bfe8 Generalize the SMBus IO Enable quirk on all Intel ICHs 
This has been tested safe on every ICH since the very first one by CPU-Z.
It also solves various SMBus access issues on Mobile PCHs (like #157)
 2023-04-26 00:42:58 +02:00
Sam Demeulemeester 0fd2e4c37a Add support for Intel AlderLake-N CPUs 2023-04-24 00:29:37 +02:00
Sam Demeulemeester fa4e903509 Fix APIC Timer detection fail on some modern mobile/embedded PCH 
On some modern ULV cores (eg: Gracemont), the 2 following I/O reads to check APIC Timer working status are fused in the frontend, leading to the same value being reported twice and the code falling back to the (unusually disabled on these platforms) PIT timer.

Whether this behavior is intentional or not is unknown.

As usleep/sleep is not available at this point, a dirty delay is added between the two reads.
 2023-04-23 22:45:27 +02:00
Sam Demeulemeester 79bb781431 Better handling of big FAIL banned in case of errors 2023-03-29 18:29:59 +02:00
Sam Demeulemeester c6b04e5414 Display big banner only once 2023-03-29 17:58:12 +02:00
Sam Demeulemeester 5cbcd2046b Add 'Jade Star' & 'InnoDisk' JEDEC Manufacturers 2023-03-09 23:08:01 +01:00
Sam Demeulemeester bf0dae04bc Remove deprecated ubuntu-18.04 job 2023-03-07 00:34:31 +01:00
Sam Demeulemeester ee0c400821 [SMBUS] Add support for VIA VT8233 Southbridge 2023-02-18 19:01:59 +01:00
Sam Demeulemeester e1fc02bfe0 [SMBUS] Add support for VIA VT8233A Southbridge 2023-02-18 18:58:34 +01:00
Sam Demeulemeester a1d046fc3a Fix a typo in README.md (serial console baud rate) 2023-02-18 18:51:02 +01:00
Sam Demeulemeester c38b0cbc5f [SMBUS] Add support for nVidia nForce 3 2023-02-13 19:43:09 +01:00
Sam Demeulemeester dfc41f7196 Solve incorrect core/thread count on some VIA CPUs 
No Cyrix / VIA / CentaurHauls / Zhaoxin CPUs support HT, so disable it.
 2023-02-11 19:00:36 +01:00
Sam Demeulemeester ce2c29eddc Bump version to v6.10 2023-02-02 23:52:18 +01:00
Sam Demeulemeester b15a8bb632 Add SPD support for ATI SB400 Southbridge 2023-01-23 16:09:32 +01:00
Sam Demeulemeester 10e8435604 Add SPD support for legacy VIA Southbridges (VT82C686A/B & VT8235) 
(From PR #236)

Author: Corentin Labbe clabbe.montjoie@gmail.com
Co-developed-by: Lionel Debroux lionel_debroux@yahoo.fr
 2023-01-23 15:01:48 +01:00
Sam Demeulemeester d3d52b8a11 Add Memtest86+ Version String to Kernel Header (#75) 2023-01-03 01:35:51 +01:00
Sam Demeulemeester da7b9b955d Move Memtest86+ version number to an external file (along with the the latest GIT commit hash) (#75) 2023-01-03 00:39:10 +01:00
Sam Demeulemeester 036922ab26 Bump version to v6.01 2022-12-30 16:41:28 +01:00
Sam Demeulemeester 9a86f115f4 Add 'press any key to remove' message on banner 
By default, don't re-display FAIL banner after it has been discarded (#130 & #173)
Add an option to re-display FAIL banner even if previously discarded
 2022-11-27 23:34:43 +01:00
Sam Demeulemeester d3bc8fa7c2 V6.00 Final Release - Fix title '+' char shift 2022-10-23 20:21:09 +02:00
Sam Demeulemeester ddbee66c85 Fix a cast issue that broke the run time clock on (very) fast CPUs 2022-09-14 20:47:29 +02:00
Sam Demeulemeester 03a5222ee2 Add support for Zen4/AM5 DDR5 SPD 2022-09-09 18:09:13 +02:00
Sam Demeulemeester 18f12116c0 Fix a rare capacity detection issue with DDR3 modules built using 3 or 4 ranks 2022-08-29 02:50:11 +02:00
Sam Demeulemeester 385f912776 Fix date decoding issue: week 53 is actually valid for some years 2022-08-29 02:12:05 +02:00
Sam Demeulemeester 6799bfba3c Fix timings decoding issues with DDR3 XMP Modules. Add quirks for early modules based on XMP Draft 2022-08-29 01:59:36 +02:00
Sam Demeulemeester 02702fa8c5 Change check to be sure Extended Topology Information (CPUID.0BH:EBX[15:0]) is supported 2022-08-15 22:26:22 +02:00
Sam Demeulemeester 8a3cac8133 Fix an issue while detection Core topology on Core 2 CPU. 
Some CPU like Intel Yorkfield (Core 2 Quad) reports max CPUID > 0xB but doesn't support CPUID = 0xB. Check x2apic flag to be sure CPUID 0xB is supported. If not, fallback to older detection method
 2022-07-26 20:02:58 +02:00
Sam Demeulemeester 740df34656 Remove now useless IMC check to allow temperature reporting on more older CPUs 2022-07-23 23:59:49 +02:00
Sam Demeulemeester cf156adc4a Solve an issue with Core 2 Duo/Quad and same gen CPUs, where HTT flag is enabled in CPUID while the CPU does not support SMT. (#125 #129) 
Now compare the number of physical core with the number of reserved APIC to check if SMT is really available or not
 2022-07-23 23:47:06 +02:00
Sam Demeulemeester 53f61e6b87 Add 'Heoriady' and 'Golden Empire' to the list of known JEDEC Manufacturers for SPD decoding (#22) 2022-07-23 23:01:53 +02:00
Sam Demeulemeester 37cb966f39 Version change to 6.00 Beta 3 (v6.00-beta3) 2022-07-17 22:31:47 +02:00
Sam Demeulemeester 187bc8609e Add support for nForce 410/430 & 680a/680i/780i/790i chipsets (tested) 2022-07-17 20:28:58 +02:00
Sam Demeulemeester 6b998e82e7 [TTY/Serial] Always use absolute positioning instead of relying on CR-LF 2022-06-19 16:47:10 +02:00
Sam Demeulemeester 680e6ad79b Typo on smp.c (missing ;) 2022-06-19 16:39:03 +02:00
Sam Demeulemeester 231b389b3c Various minor cosmetic changes on acpi.c/h (mainly comments and code format) 2022-06-19 16:39:03 +02:00
Sam Demeulemeester a5576974cf Add ACPI Timer as the primary TSC correction source and PIT Timer as fallback 2022-06-19 16:39:03 +02:00
Sam Demeulemeester eac4d03462 Parse FADT to find ACPI Timer Base Address and specs 2022-06-19 16:39:03 +02:00
Sam Demeulemeester cee2d32766 Add a few ACPI Tables Signature that could be useful later 2022-06-19 16:39:03 +02:00
Sam Demeulemeester 221a66da1a Split ACPI Functions from SMP functions. 
Add ACPI Table detection for FADT & HPET (as we need better timers)
 2022-06-19 16:39:03 +02:00